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A summary commit of all 2711-related work by many people: * Change OSC to 54MHz * Add L2 read/writ latency * Add GIC support and unconditionally setup the arch timer prescale * Don't enable the data cache before the MMU is enabled. * Enable the Cache after setting SMP bit. Cortex A72 manual 4.3.67 says says SMP must be set before enabling the cache. Probably doesn't make any real difference. N.B. armstub8-32 is for 2710 only and armstub8-32-gic is for 2711, i.e. the GIC flag is also effectively a 2711 flag. Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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@@ -29,10 +29,12 @@ | |
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#define BIT(x) (1 << (x)) | ||
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#define LOCAL_CONTROL 0x40000000 | ||
#define LOCAL_PRESCALER 0x40000008 | ||
#define LOCAL_CONTROL 0xff800000 | ||
#define LOCAL_PRESCALER 0xff800008 | ||
#define GIC_DISTB 0xff841000 | ||
#define GIC_CPUB 0xff842000 | ||
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#define OSC_FREQ 19200000 | ||
#define OSC_FREQ 54000000 | ||
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#define SCR_RW BIT(10) | ||
#define SCR_HCE BIT(8) | ||
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@@ -54,6 +56,15 @@ | |
#define SPSR_EL3_VAL \ | ||
(SPSR_EL3_D | SPSR_EL3_A | SPSR_EL3_I | SPSR_EL3_F | SPSR_EL3_MODE_EL2H) | ||
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#define L2CTLR_EL1 S3_1_C11_C0_2 | ||
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#define GICC_CTRLR 0x0 | ||
#define GICC_PMR 0x4 | ||
#define IT_NR 0x8 // Number of interrupt enable registers (256 total irqs) | ||
#define GICD_CTRLR 0x0 | ||
#define GICD_IGROUPR 0x80 | ||
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.globl _start | ||
_start: | ||
/* | ||
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@@ -67,6 +78,12 @@ _start: | |
mov w1, 0x80000000 | ||
str w1, [x0, #(LOCAL_PRESCALER - LOCAL_CONTROL)] | ||
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/* Set L2 read/write cache latency to 2 */ | ||
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mrs x0, L2CTLR_EL1 | ||
mov x1, #0x22 | ||
orr x0, x0, x1 | ||
msr L2CTLR_EL1, x0 | ||
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/* Set up CNTFRQ_EL0 */ | ||
ldr x0, =OSC_FREQ | ||
msr CNTFRQ_EL0, x0 | ||
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@@ -87,6 +104,9 @@ _start: | |
mov x0, #CPUECTLR_EL1_SMPEN | ||
msr CPUECTLR_EL1, x0 | ||
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#ifdef GIC | ||
bl setup_gic | ||
#endif | ||
/* | ||
* Set up SCTLR_EL2 | ||
* All set bits below are res1. LE, no WXN/I/SA/C/A/M | ||
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@@ -162,5 +182,33 @@ kernel_entry32: | |
.word 0x0 | ||
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.org 0x100 | ||
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#ifdef GIC | ||
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setup_gic: // Called from secure mode - set all interrupts to group 1 and enable. | ||
mrs x0, MPIDR_EL1 | ||
ldr x2, =GIC_DISTB | ||
tst x0, #0x3 | ||
b.eq 2f // primary core | ||
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mov w0, #3 // Enable group 0 and 1 IRQs from distributor | ||
str w0, [x2, #GICD_CTRLR] | ||
2: | ||
add x1, x2, #(GIC_CPUB - GIC_DISTB) | ||
mov w0, #0x1e7 | ||
str w0, [x1, #GICC_CTRLR] // Enable group 1 IRQs from CPU interface | ||
mov w0, #0xff | ||
str w0, [x1, #GICC_PMR] // priority mask | ||
add x2, x2, #GICD_IGROUPR | ||
mov x0, #(IT_NR * 4) | ||
mov w1, #~0 // group 1 all the things | ||
3: | ||
subs x0, x0, #4 | ||
str w1, [x2, x0] | ||
b.ne 3b | ||
ret | ||
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#endif | ||
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.globl dtb_space | ||
dtb_space: |
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