-
Notifications
You must be signed in to change notification settings - Fork 0
Home
An external Z80 Card for Amstrad CPC Computers
This is a card for test and development work on the Amstrad CPC computer. The card fits any expansion backplane and relocates the CPC's processor into an external Zero Insertion Force (ZIF) socket.
The card is intended for development of an alternative FPGA-based CPC processor using existing dev boards, to add performance and additional features while remaining fully Z80 and CPC software compatible.
As a secondary purpose, the external ZIF socket makes it easy to swap out the CPU for application testing of old Z80 ICs using the CPC.
The project has been built and tested. All code is open sourced and made available under the GPL 3.0 license.
Before using the card you need to open up the computer and remove the Z80 CPU from the motherboard. The CPU can be relocated to the ZIF socket and the computer powered up as normal.
The board has a 50 way box header connection compatible with all modern expansion boards (e.g. see my other projects) or can be directly plugged into an IDC connector on a ribbon cable connected to the CPC edge connector.
The board has a number of features provided for experimentation with different CPU types:
- clock conditioning options including a low pass filter and various Schmitt Trigger paths
- switchable current limiting resistors on key paths to improve compatibility of CPC 464/664 RAM cards
- a fully labelled 40 pin header for connecting logic analyzers or oscilloscopes
- link pins for CPU current measurement or alternative power supply
- a system reset button
Various combinations of clock conditioning are possible using IC1 (a schmitt trigger logic IC) and a low pass filter (LPF) constructed from an in-line 100ohm resistor and a 47pF capacitor.
The 4 pin DIP switch DIP_1 chooses between the clock conditioning options
- DIP4 - ON switches in a 47pF capacitor on the incoming clock to make a low pass filter for noise rejection ; leaving it open excludes the capacitor
- DIP3 - ON drives the CPC clock in signal (with or without the LPF) directly to the CPU
- DIP2 - ON selects a slightly delayed clock after passing through a schmitt trigger circuit
- DIP1 - ON selects a clock with a delayed rising edge to improve glitch rejection further
One and only one of DIP 1,2 or 3 should be switched ON at any time.
DIP4 can be used in conjunction with any of the other settings.
Current limit resistors are provided inline for 4 key CPU output signals. These resistors can be bypassed (short-circuited) when the corresponding switch in DIP_0 is switched to the ON position as follows:
- DIP1 - A15
- DIP2 - A14
- DIP3 - MREQ*
- DIP4 - RD*
On a 6128 all switches can be left ON (bypass or short circuit the resistors), but really it doesn't matter whether ON or OFF.
On a 664/464 with an external RAM board the switches should be left in the OFF position so that the resistors are not bypassed. External RAM boards for these machines all overdrive some or all of these signals. The current limiting resistors improve compatibility of these boards with later CPUs which may have stronger output drivers than the original NMOS Z80 parts. Modern FPGAs in particular can have very strong output drivers.
The value of the current limiting resistors can be changed: 330ohm is the suggested starting value but higher values may be advisable and need some evaluation.
There are already pull-ups on the motherboard for the active low control inputs close to the original CPU socket. The external card provides additional local pull-ups for these signals in case of noise/crosstalk issues due to the remote location of the CPU. (There are very few ground wires in the ribbon cable connection to the expansion board for example, so signals travel for some distance in close proximity.)
The local pull-ups should have relatively high values - 100Kohms is the suggested starting point.
A tactile button is provided which can trigger a system reset by grounding the Amstrads BUSRESET signal momentarily. This can save a lot of power-cycling during development work.
The link VDDLNK should be closed in normal operation. This is simply a connection for the 5V signal from the edge connector to be used to power the board.
During testing the link pins make it easy to put an ammeter in-line with the supply to measure CPU operating current.
Alternatively by leaving the link open the positive terminal of a lab supply can be connected to the upper pin and the negative terminal connected to one of the ground points to bring in external power.
A fully labelled 40 pin header is provided at the top of the board for easy connection of oscilloscope or logic analyzer probes. This is specifically intended for hookup of a Sigrok compatible logic analyzer for capturing wave traces which can then be examined using the Z80 Protocol Analyzer.
PCBs for this card can be bought directly from SeeedStudio in packs of 10 for around £15 (including postage) via my SeeedStudio Fusion Gallery Pages.
Component | Value | Note |
---|---|---|
IC_1 | 74AHCT132 | Quad 2 input NAND Schmitt trigger inputs |
R100K_0..5 | 100K Resistor | local pullups for active low control signals |
R330_0..3 | 330 ohm Resistors | Current limiting resistors for use with CPC464/664 RAM expansions |
R47K_0 | 47K Resistor | Pull up resistor for BUSRESET button |
R100_0 | 100 ohm resistor | In-line resistor for clock low pass filter |
CAP47PF | 47 pf capacitor | Ceramic cap for clock line low pass filter |
CAP100N_1..3 | 0.1uF Cap | Film, ceramic or tantalum decoupling caps for the CPU and IC_1 |
CAP22UF | 22 uF Cap | Electrolytic cap for decoupling reservoir |
SKT_1 | 40 Pin ZIF socket |