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CPC Sixrom Card
![](https://github.com/revaldinho/cpc_ram_expansion/raw/master/img/CPC_SIXROM_photo1.jpg)
This project is a CPLD-based ROM expansion board. Although only 3 sockets are provided each can be filled with a 'double size' EEPROM to provide the equivalent of 6 classic 16KByte Amstrad ROMs.
The board will co-exist with other ROM cards and uses DIP switches to enable or disable ROMs individually and to select how the ROMs on the card will be numbered to avoid clashes with other cards.
Each ROM socket can take
- a 2764 8K EPROM
- a 27128 16K EPROM (the classic AMSTRAD ROM size)
- a 28C256 32K EEPROM
- a 27256 32K EPROM
The standard CPLD firmware is optimized for use with 28C256 EEPROMs. Each of these can hold two classic ROMs which are mapped into the upper and lower address ranges for the socket and can be enabled or disabled individually.
When using a 2764 or 27128 the ROM selection switch (see below) should be set to select only the low ROM for that socket to avoid the ROM appearing twice in the Amstrad's address space.
A 27256 EPROM can also hold two classic ROMs but, with the standard CPLD firmware, only half of the ROM can be used because these parts are not pin compatible with the preferred 28C256 EEPROM. So, with the standard firmware these parts can be used to hold one classic ROM which is usually programmed in both upper and lower halves of the IC. The DIP switches should be set then to enable only the upper half.
DIP switches 1-6 are used to enable ROMs according to the following table
DIP Switch | ON |
---|---|
1 | enable lower ROM SKT01 |
2 | enable upper ROM SKT01 |
3 | enable lower ROM SKT23 |
4 | enable upper ROM SKT23 |
5 | enable lower ROM SKT45 |
6 | enable upper ROM SKT45 |
DIP switches 7-8 select the ROM numbers to be assigned to each socket as follows
DIP8 | DIP7 | SKT01 | SKT23 | SKT45 | Comment |
---|---|---|---|---|---|
OFF | OFF | Lower ROM, ROM 0 [BASIC] | ROM 1, ROM 2 | ROM 3, ROM 4 | Lower ROM and BASIC replacement and first ROM bank |
OFF | ON | Lower ROM, ROM 0 | ROM 10, ROM 11 | ROM 12, ROM 13 | FutureOS ROM configuration with optional FOS Boot ROM in Lower ROM position (or Lower ROM/BASIC replacement) |
ON | OFF | ROM 1, ROM 2 | ROM 3, ROM 4 | ROM 5, ROM 6 | ROMs 1-6 in first ROM bank, no lower ROM or Firmware replacement |
ON | ON | ROM 8, ROM 9 | ROM 10, ROM 11 | ROM 12, ROM 13 | ROMs 8-13 in second ROM bank, still FOS compatible |
All programs and data files in this project are made available under the terms of the GNU General Public License v3.
![](https://github.com/revaldinho/cpc_ram_expansion/raw/master/img/CPC_SIXROM_place.png)