Redefine rws bit field type (#101, rggen/rggen#184)

* rename bit field types

* rol -> rohw
* rws -> rwhw

* redefine rws bit field type

lib/rggen/systemverilog/ral.rb

@@ -23,11 +23,11 @@
     'ral/register/type/indirect',
     'ral/bit_field/type',
     'ral/bit_field/type/custom',
-    'ral/bit_field/type/rof_rol',
+    'ral/bit_field/type/rof_rohw',
     'ral/bit_field/type/rotrg_rwtrg_wotrg',
     'ral/bit_field/type/row0trg_row1trg_w0trg_w1trg',
     'ral/bit_field/type/rowo_rowotrg',
-    'ral/bit_field/type/rwc_rws',
+    'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
 end

lib/rggen/systemverilog/ral/bit_field/type/rof_rohw.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rof, :rohw]) do
+  sv_ral { access 'RO' }
+end

lib/rggen/systemverilog/ral/bit_field/type/rwc_rwhw_rws.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwc, :rwhw, :rws]) do
+  sv_ral { access 'RW' }
+end

lib/rggen/systemverilog/rtl.rb

@@ -38,13 +38,14 @@
     'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'rtl/bit_field/type/ro_rotrg',
     'rtl/bit_field/type/rof',
-    'rtl/bit_field/type/rol',
+    'rtl/bit_field/type/rohw',
     'rtl/bit_field/type/row0trg_row1trg',
     'rtl/bit_field/type/rowo_rowotrg',
     'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
     'rtl/bit_field/type/rw_rwtrg_w1',
     'rtl/bit_field/type/rwc',
     'rtl/bit_field/type/rwe_rwl',
+    'rtl/bit_field/type/rwhw',
     'rtl/bit_field/type/rws',
     'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
     'rtl/bit_field/type/w0t_w1t',

lib/rggen/systemverilog/rtl/bit_field/type/rol.erb → lib/rggen/systemverilog/rtl/bit_field/type/rohw.erb

@@ -9,7 +9,7 @@ rggen_bit_field #(
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= latch_signal %>),
+  .i_hw_write_enable  (<%= valid_signal %>),
   .i_hw_write_data    (<%= value_in[loop_variables] %>),
   .i_hw_set           ('0),
   .i_hw_clear         ('0),

lib/rggen/systemverilog/rtl/bit_field/type/rol.rb → lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb

@@ -1,11 +1,11 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rol) do
+RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
   sv_rtl do
     build do
       unless bit_field.reference?
-        input :latch, {
-          name: "i_#{full_name}_latch", width: 1,
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
           array_size: array_size, array_format: array_port_format
         }
       end
@@ -23,8 +23,8 @@
 
     private
 
-    def latch_signal
-      reference_bit_field || latch[loop_variables]
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
     end
   end
 end

lib/rggen/systemverilog/rtl/bit_field/type/rwhw.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .o_write_trigger    (),
+  .o_read_trigger     (),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= valid_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -0,0 +1,30 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
+  sv_rtl do
+    build do
+      unless bit_field.reference?
+        input :valid, {
+          name: "i_#{full_name}_valid", width: 1,
+          array_size: array_size, array_format: array_port_format
+        }
+      end
+      input :value_in, {
+        name: "i_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+      output :value_out, {
+        name: "o_#{full_name}", width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def valid_signal
+      reference_bit_field || valid[loop_variables]
+    end
+  end
+end

lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,16 +1,17 @@
 rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_SET_WIDTH   (1)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .bit_field_if       (<%= bit_field_if %>),
   .o_write_trigger    (),
   .o_read_trigger     (),
   .i_sw_write_enable  ('1),
-  .i_hw_write_enable  (<%= set_signal %>),
-  .i_hw_write_data    (<%= value_in[loop_variables] %>),
-  .i_hw_set           ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set_signal %>),
   .i_hw_clear         ('0),
   .i_value            ('0),
   .i_mask             ('1),

lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -9,10 +9,6 @@
           array_size: array_size, array_format: array_port_format
         }
       end
-      input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
-      }
       output :value_out, {
         name: "o_#{full_name}", width: width,
         array_size: array_size, array_format: array_port_format

spec/rggen/systemverilog/ral/bit_field/type/rol_spec.rb → spec/rggen/systemverilog/ral/bit_field/type/rohw_spec.rb

@@ -1,19 +1,19 @@
 # frozen_string_literal: true
 
-RSpec.describe 'bit_field/type/rwl' do
+RSpec.describe 'bit_field/type/rohw' do
   include_context 'clean-up builder'
   include_context 'bit field ral common'
 
   before(:all) do
-    RgGen.enable(:bit_field, :type, [:rw, :rol])
+    RgGen.enable(:bit_field, :type, [:rw, :rohw])
   end
 
   specify 'アクセス属性はRO' do
     sv_ral = create_sv_ral do
       register do
         name 'register_0'
-        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rol; initial_value 0 }
-        bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rol; initial_value 0; reference 'register_1.bit_field_0' }
+        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rohw; initial_value 0 }
+        bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rohw; initial_value 0; reference 'register_1.bit_field_0' }
       end
 
       register do

spec/rggen/systemverilog/ral/bit_field/type/rwhw_spec.rb

@@ -0,0 +1,29 @@
+
+# frozen_string_literal: true
+
+RSpec.describe 'bit_field/type/rwhw' do
+  include_context 'clean-up builder'
+  include_context 'bit field ral common'
+
+  before(:all) do
+    RgGen.enable(:bit_field, :type, [:rw, :rwhw])
+  end
+
+  specify 'アクセス属性はRW' do
+    sv_ral = create_sv_ral do
+      register do
+        name 'register_0'
+        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rwhw; initial_value 0 }
+        bit_field { name 'bit_field_1'; bit_assignment lsb: 1; type :rwhw; initial_value 0; reference 'register_1.bit_field_0' }
+      end
+
+      register do
+        name 'register_1'
+        bit_field { name 'bit_field_0'; bit_assignment lsb: 0; type :rw; initial_value 0 }
+      end
+    end
+
+    expect(sv_ral.bit_fields[0].access).to eq 'RW'
+    expect(sv_ral.bit_fields[1].access).to eq 'RW'
+  end
+end