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Redefine rws bit field type #184

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taichi-ishitani opened this issue Jan 18, 2024 · 0 comments
Closed

Redefine rws bit field type #184

taichi-ishitani opened this issue Jan 18, 2024 · 0 comments

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@taichi-ishitani
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The set signal of rws bit field type acts as a hw write port and this behavior is not matched with other xxs bit field types.
Therefore, bit field value of rws should also be set to 1 like other xxs bit field types.

To do this change, the bit field types below should be renamed.
(hw means hardware write.)

  • rws -> rwhw
  • rol -> rohw
@taichi-ishitani taichi-ishitani mentioned this issue Jan 20, 2024
Merged
taichi-ishitani added a commit to rggen/rggen-default-register-map that referenced this issue Jan 20, 2024
@taichi-ishitani
Redefine rws bit field type (#66, rggen/rggen#184)
8b18c3b 
* rename bit field types

* rol -> rohw
* rws -> rwhw

* redefine rws bit field type
taichi-ishitani added a commit to rggen/rggen-sample that referenced this issue Jan 21, 2024
@taichi-ishitani
rename bit field type name
693b250 
* rol -> rohw
* rws -> rwhw

(refs: rggen/rggen#184)
taichi-ishitani added a commit to rggen/rggen-sample that referenced this issue Jan 22, 2024
@taichi-ishitani
redefine rws bit field type
7405c00 
(refs: rggen/rggen#184)
@taichi-ishitani taichi-ishitani mentioned this issue Jan 22, 2024
Merged
taichi-ishitani added a commit to rggen/rggen-systemverilog that referenced this issue Jan 22, 2024
@taichi-ishitani
Redefine rws bit field type (#101, rggen/rggen#184)
f127675 
* rename bit field types

* rol -> rohw
* rws -> rwhw

* redefine rws bit field type
This was referenced Jan 22, 2024
Merged
Merged
taichi-ishitani added a commit to rggen/rggen-verilog that referenced this issue Jan 22, 2024
@taichi-ishitani
Redefine rws bit field type (#41, rggen/rggen#184)
b238b33 
* rename bit field type name

* rol -> rohw
* rws -> rwhw

* redefine rws bit field type
taichi-ishitani added a commit to rggen/rggen-vhdl that referenced this issue Jan 22, 2024
@taichi-ishitani
Redefine rws bit field type (#28, rggen/rggen#184)
3f7f997 
* rename bit field type name

* rol -> rohw
* rws -> rwhw

* redefine rws bit field type
taichi-ishitani added a commit to rggen/rggen-sample-testbench that referenced this issue Jan 22, 2024
@taichi-ishitani
update sample CSR modules
9267e0a 
(refs: rggen/rggen#184)
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