fetch: Almost done

.gitignore

@@ -5,3 +5,7 @@
 *.vvp
 *.vcd
 disasm.S
+*.vec
+*.log
+*.bit
+

scripts/kamikaze_test/config.v

@@ -0,0 +1 @@
+`define FPGA_ARCH_ANLOGIC_AL3

scripts/kamikaze_test/kamikaze_test.al

@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Project>
+    <Project_Created_Time>2017-02-11 13:20:21</Project_Created_Time>
+    <Name>kamikaze_test</Name>
+    <HardWare>
+        <Family>AL3</Family>
+        <Device>AL3A10BG256C7</Device>
+    </HardWare>
+    <Source_Files>
+        <Verilog>
+            <File>../../src/top.v</File>
+            <File>../../src/kamikaze.v</File>
+            <File>../../src/fetch.v</File>
+            <File>config.v</File>
+        </Verilog>
+        <ADC_FILE/>
+        <SDC_FILE/>
+        <CWC_FILE/>
+    </Source_Files>
+    <TOP_MODULE>
+        <LABEL/>
+        <MODULE>top</MODULE>
+        <CREATEINDEX>auto</CREATEINDEX>
+    </TOP_MODULE>
+    <Project_Settings>
+        <Current_Step>0</Current_Step>
+        <SRC-Last-Read/>
+        <SLC-Last-Read/>
+        <SDC-Last-Read></SDC-Last-Read>
+    </Project_Settings>
+</Project>

src/fetch.v

@@ -3,82 +3,112 @@ module kamikaze_fetch(clk_i,
 		im_addr_o,
 		im_data_i,
 		instr_o,
-		instr_valid_o);
+		instr_valid_o,
+		is_compressed_instr_o);
 	input clk_i;
 	input rst_i;
-	output reg [31:0] im_addr_o;
-	input [31:0] im_data_i;
-	reg [31:0] pc;
-	reg [2:0] pc_add;
+	input [31:0] im_data_i; 
 	output reg [31:0] instr_o;
-	reg [31:0] last_instr;
-	reg is_compressed_instr;
-	reg fetch_start;
+	output [31:0] im_addr_o;
 	output reg instr_valid_o;
+	output is_compressed_instr_o;
 
 	wire [30:0] word_address = im_addr_o[31:2];
-	reg [31:0] new_pc;
 
-	localparam CPU_START = 32'h0;
+	reg [31:0] pc;
+	reg [31:0] pc_4;
+	reg [2:0] pc_add;
+	reg [2:0] pc_add_prev;
+
+
+	reg [31:0] last_instr; /* 一级缓冲 */
+	reg is_compressed_instr;
+	reg fetch_start;	
+
+	assign is_compressed_instr_o = is_compressed_instr;
+
+	localparam CPU_START = 32'h0; /* 启动地址 */
+
+	assign im_addr_o = pc_4[1]? (pc_4 + 2'b10): pc_4; /* 舍入 */
+	assign stall_requiring = (pc_add_prev == 2) && (pc[1:0] == 2'b00); /* 16位对齐等待，防止冲数据 */
+
 
 	always @(posedge clk_i or negedge rst_i)
 	begin
 		if(!rst_i)
 		begin
-			im_addr_o <= CPU_START;
-			pc <= CPU_START;/* PC比im_addr_o滞后1 CLK */
+			pc_4 <= CPU_START;
+			pc <= CPU_START;/* PC 比 im_addr_o 滞后1 CLK */
 			fetch_start <= 0;
+			pc_add_prev <= 4;
+			last_instr <= 32'h0;
 		end
 		else
 		begin
 			if(fetch_start == 1'b0)
 			begin
-				fetch_start <= 1'b1;
-				im_addr_o <= im_addr_o + 16'h4;
+				fetch_start <= 1'b1; /* 取 0 指令 */
+				pc_4 <= pc_4 + 16'h4;
 			end
 			else
 			begin
-				//im_addr_o <= im_addr_o + pc_add;
-				/*if(im_addr_o > new_pc)
-					im_addr_o <= new_pc;*/
-				im_addr_o <= new_pc + (is_compressed_instr? 4: 6);
-				if(new_pc > pc)
-					pc <= new_pc;
-				last_instr <= im_data_i;
+				pc_4 <= pc_4 + pc_add;
+				pc <= pc + pc_add;
+
+				if(!stall_requiring)
+					last_instr <= im_data_i;
+
+				pc_add_prev <= pc_add;
 			end
 		end
 	end
 
 	always @*
 	begin
-		if(pc[1:0] == 2'b00) /* |COMP|COMP| */
-			if(last_instr[1:0] == 2'h3)
-				is_compressed_instr <= 0;
-			else
-				is_compressed_instr <= 1;
-		else
+		if(pc[1:0] == 2'b00)
 		begin
-			if(last_instr[17:16] == 2'h3)
-				is_compressed_instr <= 0;
+			if(stall_requiring)
+			begin
+				if(last_instr[1:0] != 2'b11) /* 对齐的压缩指令 */
+				begin
+					is_compressed_instr <= 1;
+					instr_o = last_instr[15:0];
+				end
+				else
+				begin
+					is_compressed_instr <= 0;
+					instr_o = last_instr[31:0];
+				end
+			end
 			else
-				is_compressed_instr <= 1; 
+			begin
+				if(im_data_i[1:0] != 2'b11) /* 对齐的压缩指令 */
+				begin
+					is_compressed_instr <= 1;
+					instr_o = im_data_i[15:0];
+				end
+				else
+				begin
+					is_compressed_instr <= 0;
+					instr_o = im_data_i[31:0];
+				end
+			end
 		end
-
-		/*if(pc[1:0] == 2'b00)
-			if(is_compressed_instr)
-				instr_o <= im_data_i[15:0];
-			else
-				instr_o <= im_data_i[31:0];
 		else
-			if(is_compressed_instr)
-				instr_o <= last_instr[31:16];
-			else
-				instr_o <= {im_data_i[15:0], last_instr[31:16]};*/
-
-
+		begin //pc[1:0] == 10
+			if(last_instr[17:16] != 2'b11) /* 不对齐的压缩指令 */
+			begin
+				is_compressed_instr <= 1;
+				instr_o = last_instr[31:16];
+			end
+			else			/* 不对齐的非压缩指令 */
+			begin
+				is_compressed_instr <= 0;
+				instr_o = {im_data_i[15:0], last_instr[31:16]};
+			end
+		end
+
 		pc_add = is_compressed_instr? 2: 4;
-		new_pc <= pc + pc_add;	
 	end
 
-
 endmodule

src/top.v

@@ -1,12 +1,14 @@
 module top(clk_i, rst_i, io_o, trap);
 	input clk_i;
 	input rst_i;
-	output reg [7:0] io_o;
+	output [7:0] io_o;
 	output trap;
-
+
+`ifndef FPGA_ARCH_ANLOGIC_AL3	
 	localparam MEM_SIZE = 4096;
 	reg [31:0] memory [0:MEM_SIZE-1];
 	initial $readmemh("../firmware/firmware.hex", memory);
+`endif
 
 	wire [31:0] im_addr;
 	reg [31:0] im_data;
@@ -15,13 +17,17 @@ module top(clk_i, rst_i, io_o, trap);
 			.rst_i(rst_i),
 			.im_addr_o(im_addr),
 			.im_data_i(im_data));
-
+
+`ifndef FPGA_ARCH_ANLOGIC_AL3	
 	always @(posedge clk_i)
 	begin
 		if(rst_i)
 			im_data <= memory[im_addr[31:2]];
 		else
 			im_data <= 32'h0;
 	end
+`else
+		assign io_o = im_data[7:0] ^ im_data[15:7] ^ im_data[23:16] ^ im_data[31:24];
+`endif
 
 endmodule