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Fix Specification Memory Port Types (chipsalliance#2319)
Correct incorrect type specified for memories in the FIRRTL specification. This is important because the memory type determines what is a legal bundle to try to connect to a memory port. I based this off of FIRRTL accepting the following circuit: circuit MemOrder: module MemOrder: input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>} input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>} input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>} mem memory: data-type => UInt<1> depth => 8 reader => r writer => w readwriter => rw read-latency => 1 write-latency => 1 read-under-write => undefined memory.r <= r memory.w <= w memory.rw <= rw Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
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