signed/lohi signal bug fixed in rs_mul.v

ridecore · Jul 12, 2017 · 200c6a6 · 200c6a6
1 parent 112a9bf
commit 200c6a6
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/src/fpga/rs_mul.v b/src/fpga/rs_mul.v
@@ -346,9 +346,9 @@ module rs_mul
 		   .wrrftag((we1 && (waddr1 == 1)) ? wrrftag_1 : wrrftag_2),
 		   .wdstval((we1 && (waddr1 == 1)) ? wdstval_1 : wdstval_2),
 		   .wspectag((we1 && (waddr1 == 1)) ? wspectag_1 : wspectag_2),
-		   .wsrc1_signed((we1 && (waddr1 == 0)) ? wsrc1_signed_1 : wsrc1_signed_2),
-		   .wsrc2_signed((we1 && (waddr1 == 0)) ? wsrc2_signed_1 : wsrc2_signed_2),
-		   .wsel_lohi((we1 && (waddr1 == 0)) ? wsel_lohi_1 : wsel_lohi_2),
+		   .wsrc1_signed((we1 && (waddr1 == 1)) ? wsrc1_signed_1 : wsrc1_signed_2),
+		   .wsrc2_signed((we1 && (waddr1 == 1)) ? wsrc2_signed_1 : wsrc2_signed_2),
+		   .wsel_lohi((we1 && (waddr1 == 1)) ? wsel_lohi_1 : wsel_lohi_2),
 		   .we((we1 && (waddr1 == 1)) || (we2 && (waddr2 == 1))),
 		   .ex_src1(ex_src1_1),
 		   .ex_src2(ex_src2_1),