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Split core zkp kernels and rv32im kernel into seperate sys crates (#449)
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Split core zkp kernels and rv32im kernel into seperate sys crates
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jbruestle committed Mar 17, 2023
1 parent 09401c9 commit 8efc329
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Showing 22 changed files with 152 additions and 80 deletions.
2 changes: 2 additions & 0 deletions Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ members = [
"risc0/build",
"risc0/build_kernel",
"risc0/circuit/rv32im",
"risc0/circuit/rv32im-sys",
"risc0/core",
"risc0/r0vm",
"risc0/sys",
Expand All @@ -29,6 +30,7 @@ repository = "https://github.com/risc0/risc0/"
risc0-build = { version = "0.13.0", default-features = false, path = "risc0/build" }
risc0-build-kernel = { version = "0.13.0", default-features = false, path = "risc0/build_kernel" }
risc0-circuit-rv32im = { version = "0.13.0", default-features = false, path = "risc0/circuit/rv32im" }
risc0-circuit-rv32im-sys = { version = "0.13.0", default-features = false, path = "risc0/circuit/rv32im-sys" }
risc0-core = { version = "0.13.0", default-features = false, path = "risc0/core" }
risc0-sys = { version = "0.13.0", default-features = false, path = "risc0/sys" }
risc0-zeroio = { version = "0.13.0", default-features = false, path = "risc0/zeroio" }
Expand Down
23 changes: 23 additions & 0 deletions risc0/circuit/rv32im-sys/Cargo.toml
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
[package]
name = "risc0-circuit-rv32im-sys"
description = "Generated HAL code for rv32im cicuit"
version = { workspace = true }
edition = { workspace = true }
license = { workspace = true }
homepage = { workspace = true }
repository = { workspace = true }
links = "risc0-circuit-rv32im-sys"

[dependencies]
risc0-core = { workspace = true }
risc0-sys = { workspace = true }

[build-dependencies]
cc = { version = "1.0", features = ["parallel"] }
glob = "0.3"
risc0-build-kernel = { workspace = true }

[features]
default = []
cuda = []
metal = []
61 changes: 61 additions & 0 deletions risc0/circuit/rv32im-sys/build.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
// Copyright 2023 RISC Zero, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

use std::{env, path::PathBuf};

use risc0_build_kernel::{KernelBuild, KernelType};

fn main() {
build_cpu_kernels();

if env::var("CARGO_FEATURE_CUDA").is_ok() {
build_cuda_kernels();
}

if env::var("CARGO_FEATURE_METAL").is_ok() {
build_metal_kernels();
}
}

fn build_cpu_kernels() {
let srcs: Vec<PathBuf> = glob::glob("cxx/*.cpp")
.unwrap()
.map(|x| x.unwrap())
.collect();
cc::Build::new()
.cpp(true)
.debug(false)
.files(&srcs)
.flag_if_supported("/std:c++17")
.flag_if_supported("-std=c++17")
.flag_if_supported("-fno-var-tracking")
.flag_if_supported("-fno-var-tracking-assignments")
.flag_if_supported("-g0")
.compile("circuit");
for src in srcs {
println!("cargo:rerun-if-changed={}", src.display());
}
}

fn build_metal_kernels() {
KernelBuild::new(KernelType::Metal)
.file("kernels/metal/eval_check.metal")
.compile("metal_kernel");
}

fn build_cuda_kernels() {
KernelBuild::new(KernelType::Cuda)
.file("kernels/cuda/eval_check.cu")
.compile("cuda_kernel");
}
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32 changes: 32 additions & 0 deletions risc0/circuit/rv32im-sys/src/lib.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
// Copyright 2023 RISC Zero, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

pub mod ffi;

#[test]
fn eval_check_size() {
// Make sure the generated eval check/poly fp doesn't increase in
// size unexpectedly. This can sometimes happen when the layout
// of registers in the circuit changes, so we want to guard against that here.

let generated = include_str!("../cxx/poly_fp.cpp");
let lines = generated.lines().count();

const LINE_LIMIT: usize = 28100;

assert!(
lines < LINE_LIMIT,
"poly_fp.cpp is expected to be under {LINE_LIMIT} lines but has {lines} lines"
);
}
4 changes: 4 additions & 0 deletions risc0/circuit/rv32im/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@ rayon = { version = "1.5", optional = true }
rustacuda_core = { version = "0.1", optional = true }
rustacuda_derive = { version = "0.1", optional = true }
metal = { version = "0.24", optional = true }
risc0-circuit-rv32im-sys = { workspace = true, optional = true }
risc0-sys = { workspace = true, optional = true }

[target.'cfg(target_os = "zkvm")'.dependencies]
Expand All @@ -42,13 +43,15 @@ cuda = [
"dep:rustacuda_core",
"dep:rustacuda_derive",
"prove",
"risc0-circuit-rv32im-sys/cuda",
"risc0-sys/cuda",
"risc0-zkp/cuda",
"std",
]
metal = [
"dep:metal",
"prove",
"risc0-circuit-rv32im-sys/metal",
"risc0-sys/metal",
"risc0-zkp/metal"
]
Expand All @@ -57,6 +60,7 @@ prove = [
"dep:rand",
"dep:rayon",
"risc0-zkp/prove",
"risc0-circuit-rv32im-sys",
"risc0-sys",
"std"
]
Expand Down
4 changes: 2 additions & 2 deletions risc0/circuit/rv32im/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -16,12 +16,12 @@ use std::env;

fn main() {
if env::var("CARGO_FEATURE_CUDA").is_ok() {
let cuda_bin = env::var("DEP_RISC0_SYS_CUDA_KERNELS_RV32IM").unwrap();
let cuda_bin = env::var("DEP_RISC0_CIRCUIT_RV32IM_SYS_CUDA_KERNEL").unwrap();
println!("cargo:rustc-env=RV32IM_CUDA_PATH={cuda_bin}");
}

if env::var("CARGO_FEATURE_METAL").is_ok() {
let metal_bin = env::var("DEP_RISC0_SYS_METAL_KERNELS_RV32IM").unwrap();
let metal_bin = env::var("DEP_RISC0_CIRCUIT_RV32IM_SYS_METAL_KERNEL").unwrap();
println!("cargo:rustc-env=RV32IM_METAL_PATH={metal_bin}");
}
}
4 changes: 2 additions & 2 deletions risc0/circuit/rv32im/src/cpp.rs
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@
use std::{ffi::CStr, os::raw::c_void};

use anyhow::{anyhow, Result};
use risc0_core::field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem};
use risc0_sys::ffi::{
use risc0_circuit_rv32im_sys::ffi::{
get_trampoline, risc0_circuit_rv32im_poly_fp, risc0_circuit_rv32im_step_compute_accum,
risc0_circuit_rv32im_step_exec, risc0_circuit_rv32im_step_verify_accum,
risc0_circuit_rv32im_step_verify_bytes, risc0_circuit_rv32im_step_verify_mem,
risc0_circuit_string_free, risc0_circuit_string_ptr, Callback, RawError,
};
use risc0_core::field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem};
use risc0_zkp::{
adapter::{CircuitDef, CircuitStep, CircuitStepContext, CircuitStepHandler, PolyFp},
hal::cpu::SyncSlice,
Expand Down
83 changes: 26 additions & 57 deletions risc0/sys/build.rs
Original file line number Diff line number Diff line change
Expand Up @@ -12,16 +12,11 @@
// See the License for the specific language governing permissions and
// limitations under the License.

use std::{
env,
path::{Path, PathBuf},
};
use std::{env, path::Path};

use risc0_build_kernel::{KernelBuild, KernelType};

fn main() {
build_cpu_kernels();

if env::var("CARGO_FEATURE_CUDA").is_ok() {
build_cuda_kernels();
}
Expand All @@ -31,43 +26,20 @@ fn main() {
}
}

fn build_cpu_kernels() {
let srcs: Vec<PathBuf> = glob::glob("cxx/rv32im/*.cpp")
.unwrap()
.map(|x| x.unwrap())
.collect();
cc::Build::new()
.cpp(true)
.debug(false)
.files(&srcs)
.flag_if_supported("/std:c++17")
.flag_if_supported("-std=c++17")
.flag_if_supported("-fno-var-tracking")
.flag_if_supported("-fno-var-tracking-assignments")
.flag_if_supported("-g0")
.compile("circuit");
for src in srcs {
println!("cargo:rerun-if-changed={}", src.display());
}
}

fn build_cuda_kernels() {
const CUDA_KERNELS: &[(&str, &str, &[&str])] = &[
("rv32im", "eval_check.cu", &[]),
(
"zkp",
"all.cu",
&[
"eltwise.cu",
"fri.cu",
"mix.cu",
"ntt.cu",
"sha.cu",
"zk.cu",
"sha256.h",
],
),
];
const CUDA_KERNELS: &[(&str, &str, &[&str])] = &[(
"zkp",
"all.cu",
&[
"eltwise.cu",
"fri.cu",
"mix.cu",
"ntt.cu",
"sha.cu",
"zk.cu",
"sha256.h",
],
)];

let inc_path = Path::new("kernels/zkp/cuda");
for (name, src, deps) in CUDA_KERNELS {
Expand All @@ -83,21 +55,18 @@ fn build_cuda_kernels() {
}

fn build_metal_kernels() {
const METAL_KERNELS: &[(&str, &[&str])] = &[
("rv32im", &["eval_check.metal"]),
(
"zkp",
&[
"eltwise.metal",
"fri.metal",
"mix.metal",
"ntt.metal",
"poseidon.metal",
"sha.metal",
"zk.metal",
],
),
];
const METAL_KERNELS: &[(&str, &[&str])] = &[(
"zkp",
&[
"eltwise.metal",
"fri.metal",
"mix.metal",
"ntt.metal",
"poseidon.metal",
"sha.metal",
"zk.metal",
],
)];

let inc_path = Path::new("kernels/zkp/metal");
for (name, srcs) in METAL_KERNELS {
Expand Down
19 changes: 0 additions & 19 deletions risc0/sys/src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -11,22 +11,3 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

pub mod ffi;

#[test]
fn eval_check_size() {
// Make sure the generated eval check/poly fp doesn't increase in
// size unexpectedly. This can sometimes happen when the layout
// of registers in the circuit changes, so we want to guard against that here.

let generated = include_str!("../cxx/rv32im/poly_fp.cpp");
let lines = generated.lines().count();

const LINE_LIMIT: usize = 28100;

assert!(
lines < LINE_LIMIT,
"poly_fp.cpp is expected to be under {LINE_LIMIT} lines but has {lines} lines"
);
}

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