Fix compile

riscv-boom · Mar 23, 2023 · 051dbad · 051dbad
1 parent 38e1a1e
commit 051dbad
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -145,7 +145,7 @@ class BoomCustomCSRs(implicit p: Parameters) extends freechips.rocketchip.tile.C
   def disableOOO = getOrElse(chickenCSR, _.value(3), true.B)
   def marchid = CustomCSR.constant(CSRs.marchid, BigInt(2))
 
-  override def decls: Seq[CustomCSR] = super.decls +: marchid
+  override def decls: Seq[CustomCSR] = super.decls :+ marchid
 }
 
 /**