Merge pull request #136 from abejgonzalez/checkstyle-patch

Adjusted syntax according to scalastyle-config

scalastyle-config.xml

@@ -8,10 +8,8 @@
  </check>
  <check level="warning" class="org.scalastyle.file.HeaderMatchesChecker" enabled="true">
   <parameters>
-   <parameter name="header"><![CDATA[//******************************************************************************
-   // Copyright (c) 2015, The Regents of the University of California (Regents).
-   // All Rights Reserved. See LICENSE for license details.
-   //------------------------------------------------------------------------------]]></parameter>
+   <parameter name="regex">true</parameter>
+   <parameter name="header">//\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\n// Copyright \(c\) \d{4} - \d{4}, The Regents of the University of California \(Regents\).\n// All Rights Reserved. See LICENSE for license details.\n//------------------------------------------------------------------------------\n// Author: .*\n//------------------------------------------------------------------------------</parameter>
   </parameters>
  </check>
  <check enabled="false" level="warning" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker"/>
@@ -78,7 +76,7 @@
   <parameters>
    <parameter name="regex"><![CDATA[XXX]]></parameter>
   </parameters>
-  <customMessage>Found String 'XXX', please adddress the issue.</customMessage>
+  <customMessage>Found String 'XXX', please address the issue.</customMessage>
  </check>
  <check level="warning" class="org.scalastyle.scalariform.NumberOfTypesChecker" enabled="true">
   <parameters>

src/main/scala/bpu/2bc-table.scala

@@ -1,15 +1,15 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // Two-bit Counter Table
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
 //
-// Christopher Celio
-// 2016 Sept 27
-//
 // Provide a two-bit counter table for use by branch predictors. Should only be
 // updated during Commit.
 //

src/main/scala/bpu/base-only.scala

@@ -1,7 +1,10 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // RISCV BaseOnly Branch Predictor
 //------------------------------------------------------------------------------

src/main/scala/bpu/bim.scala

@@ -1,7 +1,10 @@
 //******************************************************************************
-// Copyright (c) 2018, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // Bimodal Predictor Table
 //------------------------------------------------------------------------------

src/main/scala/bpu/bpd-pipeline.scala

@@ -1,15 +1,15 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2017 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // RISCV Processor Branch Prediction Pipeline
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
 //
-// Christopher Celio
-// 2017
-//
 // Access BTB and BPD to feed predictions to the Fetch Unit.
 //
 // Stages (these are in parallel with instruction fetch):
@@ -148,7 +148,8 @@ class BranchPredictionStage(fetch_width: Int)(implicit p: Parameters) extends Bo
 //   val jmp_idx = f2_btb.bits.cfi_idx
 
    btb.io.ras_update := io.f3_ras_update
-   btb.io.ras_update.valid := false.B // TODO XXX renable RAS (f2_btb.valid || io.f3_ras_update.valid) && !io.fetch_stalled
+   btb.io.ras_update.valid := false.B // TODO XXX renable RAS (f2_btb.valid || io.f3_ras_update.valid) &&
+                                      // !io.fetch_stalled
 //   when (f2_btb.valid)
 //   {
 //      btb.io.ras_update.bits.is_call      := BpredType.isCall(f2_btb.bits.bpd_type)

src/main/scala/bpu/brpredictor.scala

@@ -1,15 +1,15 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // RISCV Branch Predictor (abstract class)
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
 //
-// Christopher Celio
-// 2015 Oct 12
-
 // provide an abstract class for branch predictors. Provides support by
 // maintaining the global history.
 //
@@ -148,7 +148,8 @@ abstract class BrPredictor(
 
    val r_f1_fetchpc = RegEnable(io.req.bits.addr, io.req.valid)
 
-   // The global history register  that will be hashed with the fetch-pc to compute tags and indices for our branch predictors.
+   // The global history register  that will be hashed with the fetch-pc to
+   // compute tags and indices for our branch predictors.
    val f0_history   = Wire(UInt(history_length.W))
    val new_history  = Wire(UInt(history_length.W))
    val r_f1_history = RegInit(0.asUInt(width=history_length.W))

src/main/scala/bpu/btb-sa.scala

@@ -1,7 +1,10 @@
 //******************************************************************************
-// Copyright (c) 2017, The Regents of the University of California (Regents).
+// Copyright (c) 2017 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // Set-associative Branch Target Buffer with RAS and BIM predictor (BTB-sa)
 //------------------------------------------------------------------------------

src/main/scala/bpu/btb.scala

@@ -1,7 +1,10 @@
 //******************************************************************************
-// Copyright (c) 2018, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // RISCV Branch Target Buffer (abstract class)
 //------------------------------------------------------------------------------

src/main/scala/bpu/dense-btb.scala

@@ -1,7 +1,10 @@
 //******************************************************************************
-// Copyright (c) 2018, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // Dense Branch Target Buffer with RAS and BIM predictor (DenseBTB)
 //------------------------------------------------------------------------------
@@ -96,8 +99,10 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
       entry
    }
 
-   // TODO: Generalize this logic to handle writing to mixed type entries based on the number of ways; Currently, the
-   // logic below assumes number of ways to be 4 and only supports writing the dense branches biased toward the lower ways
+   // TODO: Generalize this logic to handle writing to mixed type entries
+   //       based on the number of ways; Currently, the
+   // logic below assumes number of ways to be 4 and only supports writing the dense branches
+   // biased toward the lower ways
    require(nWays == 4)
    private def getBankWriteData(next_way: UInt, btb_q_entry: BTBUpdateQueueEntry) = {
       val wdata = WireInit(VecInit(Seq.fill(nWays){(0.U).asTypeOf(new BTBSetData())}))
@@ -117,7 +122,8 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
 
       when (level === 1.U) {
          wdata(1).tag      := getTag(btb_q_entry.update.pc)
-         wdata(1).offset   := btb_q_entry.update.target(min(vaddrBits-1, tag_sz+2*offset_sz+lsb_sz-1), tag_sz+offset_sz+lsb_sz)
+         wdata(1).offset   := btb_q_entry.update.target(min(vaddrBits-1, tag_sz+2*offset_sz+lsb_sz-1),
+                                                        tag_sz+offset_sz+lsb_sz)
          wdata(1).cfi_idx  := btb_q_entry.update.cfi_pc >> log2Ceil(coreInstBytes)
          wdata(1).bpd_type := btb_q_entry.update.bpd_type
          wdata(1).cfi_type := btb_q_entry.update.cfi_type
@@ -129,11 +135,14 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
       if (branch_levels > 2) {
          when (level === 2.U) {
             for (i <- 0 until 1) {
-               wdata(i).tag    := btb_q_entry.update.target((i+1)*(tag_sz+offset_sz)+lsb_sz-1, i*tag_sz+(i+1)*offset_sz+lsb_sz)
-               wdata(i).offset := btb_q_entry.update.target(i*tag_sz+(i+1)*offset_sz+lsb_sz-1, i*(tag_sz+offset_sz)+lsb_sz)
+               wdata(i).tag    := btb_q_entry.update.target((i+1)*(tag_sz+offset_sz)+lsb_sz-1,
+                                                            i*tag_sz+(i+1)*offset_sz+lsb_sz)
+               wdata(i).offset := btb_q_entry.update.target(i*tag_sz+(i+1)*offset_sz+lsb_sz-1,
+                                                            i*(tag_sz+offset_sz)+lsb_sz)
             }
             wdata(2).tag      := getTag(btb_q_entry.update.pc)
-            wdata(2).offset   := btb_q_entry.update.target(min(vaddrBits-1, 2*tag_sz + 3*offset_sz+lsb_sz-1), 2*(tag_sz+offset_sz)+lsb_sz)
+            wdata(2).offset   := btb_q_entry.update.target(min(vaddrBits-1, 2*tag_sz + 3*offset_sz+lsb_sz-1),
+                                                           2*(tag_sz+offset_sz)+lsb_sz)
             wdata(2).cfi_idx  := btb_q_entry.update.cfi_pc >> log2Ceil(coreInstBytes)
             wdata(2).bpd_type := btb_q_entry.update.bpd_type
             wdata(2).cfi_type := btb_q_entry.update.cfi_type
@@ -216,7 +225,8 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
          }
       }
 
-      val wen    = btb_update_q.io.deq.valid && !io.status_debug && (getBank(btb_update_q.io.deq.bits.update.pc) === b.U)
+      val wen    = btb_update_q.io.deq.valid && !io.status_debug &&
+                   (getBank(btb_update_q.io.deq.bits.update.pc) === b.U)
       val bmask  = if (blevel_sz > 1) ((1.U << blevel_sz) - 1.U) else 1.U
       when (!ren && wen)
       {
@@ -227,7 +237,8 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
 
          when (btb_update_q.io.deq.bits.level === 0.U) {
             valids(widx)  := valids(widx).bitSet(next_way, true.B)
-            blevels(widx) := blevels(widx) & ~(bmask << (blevel_sz.U*next_way)) | (btb_update_q.io.deq.bits.level << (blevel_sz.U*next_way))
+            blevels(widx) := blevels(widx) & ~(bmask << (blevel_sz.U*next_way)) |
+                             (btb_update_q.io.deq.bits.level << (blevel_sz.U*next_way))
          } .elsewhen (btb_update_q.io.deq.bits.level === 1.U) {
             // change only the lower two bits of valid
             valids(widx)  := (valids(widx) & 12.U) | 2.U
@@ -378,8 +389,15 @@ class DenseBTB(implicit p: Parameters) extends BoomBTB
    if (DEBUG_PRINTF)
    {
       printf("BTB predi (%c): hits:%x %d (PC= 0x%x, TARG= 0x%x %d) s2_BIM [%d %d 0x%x]\n",
-         Mux(s1_valid, Str("V"), Str("-")), hits.asUInt, true.B, RegNext(io.req.bits.addr), s1_resp_bits.target, s1_resp_bits.cfi_type,
-         bim.io.resp.valid, bim.io.resp.bits.entry_idx, bim.io.resp.bits.rowdata)
+         Mux(s1_valid, Str("V"), Str("-")),
+         hits.asUInt,
+         true.B,
+         RegNext(io.req.bits.addr),
+         s1_resp_bits.target,
+         s1_resp_bits.cfi_type,
+         bim.io.resp.valid,
+         bim.io.resp.bits.entry_idx,
+         bim.io.resp.bits.rowdata)
    }
 
    override def toString: String =

src/main/scala/bpu/gshare.scala

@@ -1,15 +1,15 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // RISCV GShare Branch Predictor
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
 //
-// Christopher Celio
-// 2015 Apr 28
-
 // Notes:
 //    - Implements gshare in a a 1r1w SRAM (need to bank to get to 1rw).
 //    - Does not rectangularize the memory.

src/main/scala/bpu/tage-table.scala

@@ -1,15 +1,14 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // TAGE Table (used by the TAGE branch predictor)
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
-//
-// Christopher Celio
-// 2016 Feb 26
-
 
 package boom.bpu
 
@@ -111,7 +110,8 @@ class TageTableWrite(fetch_width: Int, index_sz: Int, tag_sz: Int, cntr_sz: Int,
    val mispredict = Bool()
    val taken = Bool()
 
-   override def cloneType: this.type = new TageTableWrite(fetch_width, index_sz, tag_sz, cntr_sz, ubit_sz).asInstanceOf[this.type]
+   override def cloneType: this.type = new TageTableWrite(fetch_width, index_sz, tag_sz, cntr_sz,
+                                                          ubit_sz).asInstanceOf[this.type]
 }
 
 
@@ -172,7 +172,8 @@ class TageTable(
          Mux(update && !mispredicted, 1.U,
             0.U))
 
-      assert (PopCount(VecInit(allocate, update, degrade)) > 0.U, "[TageTable[" + id + "]] ubit not told to do something.")
+      assert (PopCount(VecInit(allocate, update, degrade)) > 0.U,
+              "[TageTable[" + id + "]] ubit not told to do something.")
 
       next
    }

src/main/scala/bpu/tage.scala

@@ -1,15 +1,15 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2016 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
+
 //------------------------------------------------------------------------------
 // TAGE-based Branch Predictor
 //------------------------------------------------------------------------------
 //------------------------------------------------------------------------------
 //
-// Christopher Celio
-// 2016 Feb 26
-
 // Terminology:
 //    - provider
 //       The table that provides the prediction (typically the "best" prediction).

src/main/scala/common/configs.scala

@@ -1,7 +1,9 @@
 //******************************************************************************
-// Copyright (c) 2015, The Regents of the University of California (Regents).
+// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
 // All Rights Reserved. See LICENSE for license details.
 //------------------------------------------------------------------------------
+// Author: Christopher Celio
+//------------------------------------------------------------------------------
 
 package boom.common
 
@@ -110,7 +112,8 @@ class WithMediumBooms extends Config((site, here, up) => {
          maxBrCount = 8,
          regreadLatency = 1,
          renameLatency = 2,
-         btb = BoomBTBParameters(btbsa=true, nSets=64, nWays=2, nRAS=8, tagSz=20, bypassCalls=false, rasCheckForEmpty=false),
+         btb = BoomBTBParameters(btbsa=true, nSets=64, nWays=2,
+                                 nRAS=8, tagSz=20, bypassCalls=false, rasCheckForEmpty=false),
          gshare = Some(GShareParameters(enabled=true, history_length=23, num_sets=4096)),
          nPerfCounters = 6,
          fpu = Some(freechips.rocketchip.tile.FPUParams(sfmaLatency=4, dfmaLatency=4, divSqrt=true))),
@@ -138,7 +141,8 @@ class WithMegaBooms extends Config((site, here, up) => {
          maxBrCount = 16,
          btb = BoomBTBParameters(nSets=512, nWays=4, nRAS=16, tagSz=20),
          tage = Some(TageParameters())),
-      dcache = Some(DCacheParams(rowBits = site(SystemBusKey).beatBytes*8, nSets=64, nWays=16, nMSHRs=8, nTLBEntries=32)),
+      dcache = Some(DCacheParams(rowBits = site(SystemBusKey).beatBytes*8,
+                                 nSets=64, nWays=16, nMSHRs=8, nTLBEntries=32)),
       icache = Some(ICacheParams(fetchBytes = 8*4, rowBits = site(SystemBusKey).beatBytes*8, nSets=128, nWays=4))
       )}
    // Set TL network to 128bits wide