Merge pull request #392 from riscv-boom/nouopwdata

[core] Remove redundant MicroOpWithData bundle
riscv-boom · Sep 24, 2019 · 2256eca · 2256eca
2 parents ca8a670 + 3b432be
commit 2256eca
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Showing 4 changed files with 3 additions and 14 deletions.
diff --git a/src/main/scala/common/micro-op.scala b/src/main/scala/common/micro-op.scala
@@ -184,13 +184,3 @@ class DebugStageEvents extends Bundle()
 }
 
 
-/**
- * MicroOp with data
- *
- * @param data_sz size of data to put with MicroOp
- */
-class MicroOpWithData(val data_sz: Int)(implicit p: Parameters) extends BoomBundle
-  with HasBoomUOP
-{
-  val data = UInt(data_sz.W)
-}
diff --git a/src/main/scala/exu/execution-units/execution-unit.scala b/src/main/scala/exu/execution-units/execution-unit.scala
@@ -32,7 +32,6 @@ import boom.util.{ImmGen, IsKilledByBranch, BranchKillableQueue, BoomCoreStringP
 
 /**
  * Response from Execution Unit. Bundles a MicroOp with data
- * TODO rename to something like MicroOpWithData
  *
  * @param dataWidth width of the data coming from the execution unit
  */

diff --git a/src/main/scala/exu/fp-pipeline.scala b/src/main/scala/exu/fp-pipeline.scala
@@ -43,7 +43,7 @@ class FpPipeline(implicit p: Parameters) extends BoomModule with tile.HasFPUPara
     // +1 for recoding.
     val ll_wports        = Flipped(Vec(memWidth, Decoupled(new ExeUnitResp(fLen+1))))// from memory unit
     val from_int         = Flipped(Decoupled(new ExeUnitResp(fLen+1)))// from integer RF
-    val to_sdq           = Decoupled(new MicroOpWithData(fLen))           // to Load/Store Unit
+    val to_sdq           = Decoupled(new ExeUnitResp(fLen))           // to Load/Store Unit
     val to_int           = Decoupled(new ExeUnitResp(xLen))           // to integer RF
 
     val wakeups          = Vec(numWakeupPorts, Valid(new ExeUnitResp(fLen+1)))

diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -53,7 +53,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.Str
 
 import boom.common._
-import boom.exu.{BrResolutionInfo, Exception, FuncUnitResp, CommitSignals}
+import boom.exu.{BrResolutionInfo, Exception, FuncUnitResp, CommitSignals, ExeUnitResp}
 import boom.util.{BoolToChar, AgePriorityEncoder, IsKilledByBranch, GetNewBrMask, WrapInc, IsOlder, UpdateBrMask}
 
 class LSUExeIO(implicit p: Parameters) extends BoomBundle()(p)
@@ -116,7 +116,7 @@ class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)
   val ldq_full    = Output(Vec(coreWidth, Bool()))
   val stq_full    = Output(Vec(coreWidth, Bool()))
 
-  val fp_stdata   = Flipped(Decoupled(new MicroOpWithData(fLen)))
+  val fp_stdata   = Flipped(Decoupled(new ExeUnitResp(fLen)))
 
   val commit      = Input(new CommitSignals)
   val commit_load_at_rob_head = Input(Bool())