Merge pull request #484 from riscv-boom/prober-fix

[mshr] MSHRS should not wait on prober when not to same set

src/main/scala/lsu/dcache.scala

@@ -155,6 +155,8 @@ class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
     val mshr_wb_rdy = Output(Bool()) // Should we block MSHR writebacks while we finish our own?
     val block_state = Input(new ClientMetadata())
     val lsu_release = Decoupled(new TLBundleC(edge.bundle))
+
+    val state = Output(Valid(UInt(coreMaxAddrBits.W)))
   }
 
   val (s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req ::
@@ -173,6 +175,9 @@ class BoomProbeUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCach
   val reply_coh = Mux(tag_matches, old_coh, miss_coh)
   val (is_dirty, report_param, new_coh) = reply_coh.onProbe(req.param)
 
+  io.state.valid := state =/= s_invalid
+  io.state.bits  := req.address
+
   io.req.ready := state === s_invalid
   io.rep.valid := state === s_release
   io.rep.bits := edge.ProbeAck(req, report_param)
@@ -777,7 +782,7 @@ class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModu
   metaWriteArb.io.in(1) <> prober.io.meta_write
   prober.io.mshr_rdy    := mshrs.io.probe_rdy
   prober.io.wb_rdy      := (prober.io.meta_write.bits.idx =/= wb.io.idx.bits) || !wb.io.idx.valid
-  mshrs.io.prober_idle  := prober.io.req.ready && !lrsc_valid
+  mshrs.io.prober_state := prober.io.state
 
   // refills
   when (tl_out.d.bits.source === cfg.nMSHRs.U) {

src/main/scala/lsu/mshrs.scala

@@ -63,7 +63,7 @@ class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
     val mem_grant   = Flipped(Decoupled(new TLBundleD(edge.bundle)))
     val mem_finish  = Decoupled(new TLBundleE(edge.bundle))
 
-    val prober_idle = Input(Bool())
+    val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
 
     val refill      = Decoupled(new L1DataWriteReq)
 
@@ -281,7 +281,7 @@ class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p)
       state := s_meta_read
     }
   } .elsewhen (state === s_meta_read) {
-    io.meta_read.valid := io.prober_idle || !grantack.valid
+    io.meta_read.valid := !io.prober_state.valid || !grantack.valid || (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx)
     io.meta_read.bits.idx := req_idx
     io.meta_read.bits.tag := req_tag
     io.meta_read.bits.way_en := req.way_en
@@ -525,7 +525,7 @@ class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()
     val prefetch   = Decoupled(new BoomDCacheReq)
     val wb_req     = Decoupled(new WritebackReq(edge.bundle))
 
-    val prober_idle = Input(Bool())
+    val prober_state = Input(Valid(UInt(coreMaxAddrBits.W)))
 
     val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence
 
@@ -649,7 +649,7 @@ class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()
     mshr.io.rob_pnr_idx  := io.rob_pnr_idx
     mshr.io.rob_head_idx := io.rob_head_idx
 
-    mshr.io.prober_idle  := io.prober_idle
+    mshr.io.prober_state := io.prober_state
 
     mshr.io.wb_resp      := io.wb_resp