Merge pull request #394 from riscv-boom/paramclean

[core] Remove unsupported parameters

src/main/scala/common/parameters.scala

@@ -33,14 +33,11 @@ case class BoomCoreParams(
   numStqEntries: Int = 16,
   numIntPhysRegisters: Int = 96,
   numFpPhysRegisters: Int = 64,
-  enableCustomRf: Boolean = false,
-  enableCustomRfModel: Boolean = true,
   maxBrCount: Int = 4,
   numFetchBufferEntries: Int = 16,
   enableAgePriorityIssue: Boolean = true,
   enablePrefetching: Boolean = false,
   enableFastLoadUse: Boolean = true,
-  enableBrResolutionRegister: Boolean = true,
   enableCommitMapTable: Boolean = false,
   enableFastPNR: Boolean = false,
   enableFastWakeupsToRename: Boolean = true,
@@ -59,8 +56,6 @@ case class BoomCoreParams(
   bpdRandom: Option[RandomBpdParameters] = None,
   intToFpLatency: Int = 2,
   imulLatency: Int = 3,
-  fetchLatency: Int = 4,
-  renameLatency: Int = 2,
   nPerfCounters: Int = 0,
   numRXQEntries: Int = 4,
   numRCQEntries: Int = 8,
@@ -152,8 +147,6 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
   val numRcqEntries = boomParams.numRCQEntries       // number of RoCC commit queue entries. This can be large since it just keeps a pdst
   val numLdqEntries = boomParams.numLdqEntries       // number of LAQ entries
   val numStqEntries = boomParams.numStqEntries       // number of SAQ/SDQ entries
-  val NUM_LDQ_ENTRIES = numLdqEntries // TODO Remove these after
-  val NUM_STQ_ENTRIES = numStqEntries // completion of lsu refactor.
   val maxBrCount    = boomParams.maxBrCount          // number of branches we can speculate simultaneously
   val ftqSz         = boomParams.ftq.nEntries        // number of FTQ entries
   val numFetchBufferEntries = boomParams.numFetchBufferEntries // number of instructions that stored between fetch&decode
@@ -180,12 +173,6 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
 
   val intToFpLatency = boomParams.intToFpLatency
 
-  val fetchLatency = boomParams.fetchLatency // how many cycles does fetch occupy?
-  require (fetchLatency == 4) // Only 4-cycle fetch is supported
-  val renameLatency = boomParams.renameLatency // how many cycles does rename occupy?
-
-  val enableBrResolutionRegister = boomParams.enableBrResolutionRegister
-
   //************************************
   // Issue Units
 
@@ -283,10 +270,6 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
   require ((numLdqEntries-1) > coreWidth)
   require ((numStqEntries-1) > coreWidth)
 
-  //************************************
-  // Custom Logic
-  val enableCustomRf      = boomParams.enableCustomRf
-  val enableCustomRfModel = boomParams.enableCustomRfModel
 
   //************************************
   // Other Non/Should-not-be sythesizable modules

src/main/scala/exu/core.scala

@@ -109,21 +109,13 @@ class BoomCore(implicit p: Parameters) extends BoomModule
   val issue_units      = new boom.exu.IssueUnits(numIntIssueWakeupPorts)
   val dispatcher       = Module(new BasicDispatcher)
 
-  val iregfile         = if (enableCustomRf) {
-                           Module(new RegisterFileSeqCustomArray(
+  val iregfile         = Module(new RegisterFileSynthesizable(
                              numIntPhysRegs,
                              numIrfReadPorts,
                              numIrfWritePorts + memWidth, // + memWidth for ll writebacks
                              xLen,
                              Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb
-                         } else {
-                           Module(new RegisterFileSynthesizable(
-                             numIntPhysRegs,
-                             numIrfReadPorts,
-                             numIrfWritePorts + memWidth, // + memWidth for ll writebacks
-                             xLen,
-                             Seq.fill(memWidth) {true} ++ exe_units.bypassable_write_port_mask)) // bypassable ll_wb
-                         }
+
 
   // wb arbiter for the 0th ll writeback
   // TODO: should this be a multi-arb?
@@ -272,13 +264,12 @@ class BoomCore(implicit p: Parameters) extends BoomModule
         "Issue Width           : " + issueParams.map(_.issueWidth).sum,
         "ROB Size              : " + numRobEntries,
         "Issue Window Size     : " + issueParams.map(_.numEntries) + issStr,
-        "Load/Store Unit Size  : " + NUM_LDQ_ENTRIES + "/" + NUM_STQ_ENTRIES,
+        "Load/Store Unit Size  : " + numLdqEntries + "/" + numStqEntries,
         "Num Int Phys Registers: " + numIntPhysRegs,
         "Num FP  Phys Registers: " + numFpPhysRegs,
         "Max Branch Count      : " + maxBrCount)
     + BoomCoreStringPrefix(
-        "RAS Size              : " + (if (enableBTB) boomParams.btb.nRAS else 0),
-        "Rename Stage Latency  : " + renameLatency) + "\n"
+        "RAS Size              : " + (if (enableBTB) boomParams.btb.nRAS else 0)) + "\n"
     + iregfile.toString + "\n"
     + BoomCoreStringPrefix(
         "Num Slow Wakeup Ports : " + numIrfWritePorts,

src/main/scala/exu/execution-units/functional-unit.scala

@@ -503,9 +503,7 @@ class ALUUnit(isBranchUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)
       }
     }
 
-    val br_unit =
-      if (enableBrResolutionRegister) RegInit((0.U).asTypeOf(new BranchUnitResp))
-      else Wire(new BranchUnitResp)
+    val br_unit = RegInit((0.U).asTypeOf(new BranchUnitResp))
 
 
     br_unit.take_pc := mispredict
@@ -515,9 +513,7 @@ class ALUUnit(isBranchUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)
     // Delay branch resolution a cycle for critical path reasons.
     // If the rest of "br_unit" is being registered too, then we don't need to
     // register "brinfo" here, since in that case we would be double counting.
-    val brinfo =
-      if (enableBrResolutionRegister) Wire(new BrResolutionInfo)
-      else RegInit((0.U).asTypeOf(new BrResolutionInfo))
+    val brinfo = Wire(new BrResolutionInfo)
 
     // note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
     brinfo.valid          := io.req.valid && uop.is_br_or_jmp && !uop.is_jal && !killed