Merge pull request #633 from riscv-boom/chisel356

Bump to chisel 3.5.6/latest rocket-chip

src/main/scala/common/config-mixins.scala

@@ -8,7 +8,7 @@ package boom.common
 import chisel3._
 import chisel3.util.{log2Up}
 
-import freechips.rocketchip.config.{Parameters, Config, Field}
+import org.chipsalliance.cde.config.{Parameters, Config, Field}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.{BootROMParams}
 import freechips.rocketchip.diplomacy.{SynchronousCrossing, AsynchronousCrossing, RationalCrossing}

src/main/scala/common/consts.scala

@@ -14,7 +14,7 @@ package boom.common.constants
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.Str
 import freechips.rocketchip.rocket.RVCExpander
 

src/main/scala/common/micro-op.scala

@@ -14,7 +14,7 @@ package boom.common
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.exu.FUConstants
 

src/main/scala/common/parameters.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.util._
 import freechips.rocketchip.subsystem.{MemoryPortParams}
-import freechips.rocketchip.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Parameters, Field}
 import freechips.rocketchip.devices.tilelink.{BootROMParams, CLINTParams, PLICParams}
 
 import boom.ifu._

src/main/scala/common/tile.scala

@@ -10,7 +10,7 @@ import chisel3.util.{RRArbiter, Queue}
 
 import scala.collection.mutable.{ListBuffer}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._

src/main/scala/common/types.scala

@@ -7,7 +7,7 @@ package boom.common
 
 import chisel3._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 /**
  * BOOM module that is used to add parameters to the module

src/main/scala/exu/core.scala

@@ -33,7 +33,7 @@ import java.nio.file.{Paths}
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.rocket.Instructions._
 import freechips.rocketchip.rocket.{Causes, PRV, TracedInstruction}
 import freechips.rocketchip.util.{Str, UIntIsOneOf, CoreMonitorBundle}

src/main/scala/exu/decode.scala

@@ -8,7 +8,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.rocket.Instructions._
 import freechips.rocketchip.rocket.Instructions32
 import freechips.rocketchip.rocket.CustomInstructions._

src/main/scala/exu/dispatch.scala

@@ -15,7 +15,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.common._
 import boom.util._

src/main/scala/exu/execution-units/execution-unit.scala

@@ -20,7 +20,7 @@ import scala.collection.mutable.{ArrayBuffer}
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.rocket.{BP}
 import freechips.rocketchip.tile.{XLen, RoCCCoreIO}
 import freechips.rocketchip.tile

src/main/scala/exu/execution-units/execution-units.scala

@@ -15,7 +15,7 @@ import scala.collection.mutable.{ArrayBuffer}
 
 import chisel3._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 
 import boom.common._
 import boom.util.{BoomCoreStringPrefix}

src/main/scala/exu/execution-units/fdiv.scala

@@ -13,7 +13,7 @@ package boom.exu
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile.FPConstants._
 import freechips.rocketchip.tile
 import boom.common._

src/main/scala/exu/execution-units/fpu.scala

@@ -7,7 +7,7 @@ package boom.exu
 
 import chisel3._
 import chisel3.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile.FPConstants._
 import freechips.rocketchip.tile.{FPUCtrlSigs, HasFPUParameters}
 import freechips.rocketchip.tile

src/main/scala/exu/execution-units/functional-unit.scala

@@ -19,7 +19,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util._
 import freechips.rocketchip.tile
 import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}

src/main/scala/exu/execution-units/rocc.scala

@@ -15,7 +15,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tile.{RoCCCoreIO, RoCCInstruction}
 import freechips.rocketchip.rocket._
 

src/main/scala/exu/fp-pipeline.scala

@@ -14,7 +14,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.rocket
 import freechips.rocketchip.tile
 

src/main/scala/exu/issue-units/issue-slot.scala

@@ -18,7 +18,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.common._
 import boom.util._

src/main/scala/exu/issue-units/issue-unit-age-ordered.scala

@@ -14,7 +14,7 @@ package boom.exu
 import chisel3._
 import chisel3.util.{log2Ceil, PopCount}
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.Str
 
 import FUConstants._

src/main/scala/exu/issue-units/issue-unit-unordered.scala

@@ -14,7 +14,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.Str
 
 import FUConstants._

src/main/scala/exu/issue-units/issue-unit.scala

@@ -14,7 +14,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.{Str}
 
 import boom.common._

src/main/scala/exu/register-read/func-unit-decode.scala

@@ -16,7 +16,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.uintToBitPat
 import freechips.rocketchip.rocket.CSR
 

src/main/scala/exu/register-read/regfile.scala

@@ -16,7 +16,7 @@ import scala.collection.mutable.ArrayBuffer
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.common._
 import boom.util.{BoomCoreStringPrefix}

src/main/scala/exu/register-read/register-read.scala

@@ -14,7 +14,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.common._
 import boom.util._

src/main/scala/exu/rename/rename-busytable.scala

@@ -15,7 +15,7 @@ import chisel3._
 import chisel3.util._
 import boom.common._
 import boom.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class BusyResp extends Bundle
 {

src/main/scala/exu/rename/rename-freelist.scala

@@ -15,7 +15,7 @@ import chisel3._
 import chisel3.util._
 import boom.common._
 import boom.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class RenameFreeList(
   val plWidth: Int,

src/main/scala/exu/rename/rename-maptable.scala

@@ -15,7 +15,7 @@ import chisel3._
 import chisel3.util._
 import boom.common._
 import boom.util._
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class MapReq(val lregSz: Int) extends Bundle
 {

src/main/scala/exu/rename/rename-stage.scala

@@ -20,7 +20,7 @@ package boom.exu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 import boom.common._
 import boom.util._

src/main/scala/exu/rob.scala

@@ -28,7 +28,7 @@ import scala.math.ceil
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.Str
 
 import boom.common._

src/main/scala/ifu/bpd/bim.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/btb.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/composer.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/faubtb.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/hbim.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/local.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/loop.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/predictor.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/ras.scala

@@ -9,7 +9,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.{SourceInfo}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.rocket._

src/main/scala/ifu/bpd/sw_predictor.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/tage.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/tourney.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/bpd/ubtb.scala

@@ -3,7 +3,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Field, Parameters}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 

src/main/scala/ifu/fetch-buffer.scala

@@ -16,7 +16,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.rocket.{MStatus, BP, BreakpointUnit}
 
 import boom.common._

src/main/scala/ifu/fetch-target-queue.scala

@@ -19,7 +19,7 @@ package boom.ifu
 import chisel3._
 import chisel3.util._
 
-import freechips.rocketchip.config.{Parameters}
+import org.chipsalliance.cde.config.{Parameters}
 import freechips.rocketchip.util.{Str}
 
 import boom.common._

src/main/scala/ifu/frontend.scala

@@ -15,7 +15,7 @@ import chisel3._
 import chisel3.util._
 import chisel3.internal.sourceinfo.{SourceInfo}
 
-import freechips.rocketchip.config._
+import org.chipsalliance.cde.config._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.rocket._