Fix syntax for refactor

src/main/scala/exu/core.scala

@@ -160,8 +160,9 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    val brunit_idx = exe_units.br_unit_idx
    br_unit <> exe_units.br_unit_io
 
-   for (eu <- exe_units) {
-      eu.io.brinfo := br_unit.brinfo
+   for (eu <- exe_units)
+   {
+      eu.io.brinfo        := br_unit.brinfo
       eu.io.com_exception := rob.io.flush.valid
    }
    if (usingFPU)

src/main/scala/exu/execution_units.scala

@@ -173,7 +173,7 @@ class ExecutionUnits(fpu: Boolean)(implicit val p: Parameters) extends HasBoomCo
    require (exe_units.length != 0)
    if (!fpu)
    {
-      // if this is for FPU units, we don't need a memory unit (or other integer units)..
+      // if this is for FPU units, we don't need a memory unit (or other integer units).
       require (exe_units.map(_.has_mem).reduce(_|_), "Datapath is missing a memory unit.")
       require (exe_units.map(_.has_mul).reduce(_|_), "Datapath is missing a multiplier.")
       require (exe_units.map(_.has_div).reduce(_|_), "Datapath is missing a divider.")

src/main/scala/exu/fppipeline.scala

@@ -65,8 +65,8 @@ class FpPipeline(implicit p: Parameters) extends BoomModule()(p) with tile.HasFP
                                  exe_units.num_frf_read_ports,
                                  exe_units.num_frf_write_ports + 1, // + 1 for ll writeback
                                  fLen+1,
-                                 // No bypassing for FP
-                                 Seq(false) ++ (0 until exe_units.num_frf_write_ports).map(x=>false)
+                                 // No bypassing for any FP units, + 1 for ll_wb
+                                 Seq.fill(exe_units.num_frf_write_ports + 1){ false }
                                  ))
    val fregister_read   = Module(new RegisterRead(
                            issue_unit.issue_width,