FiX debug not being reflected in trace.priv

riscv-boom · Apr 13, 2023 · 679f358 · 679f358
1 parent 49e8d04
commit 679f358
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/src/main/scala/exu/core.scala b/src/main/scala/exu/core.scala
@@ -1463,7 +1463,7 @@ class BoomCore()(implicit p: Parameters) extends BoomModule
       // }
 
       // These csr signals do not exactly match up with the ROB commit signals.
-      io.trace(w).priv       := RegNext(csr.io.status.prv)
+      io.trace(w).priv       := RegNext(Cat(RegNext(csr.io.status.debug), csr.io.status.prv))
       // Can determine if it is an interrupt or not based on the MSB of the cause
       io.trace(w).exception  := RegNext(rob.io.com_xcpt.valid && !rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B
       io.trace(w).interrupt  := RegNext(rob.io.com_xcpt.valid && rob.io.com_xcpt.bits.cause(xLen - 1)) && (w == 0).B