Merge pull request #494 from EECS-NTNU/updated-memory-documentation

Updated LSU documentation and diagram
riscv-boom · Oct 15, 2020 · 840d4e5 · 840d4e5
2 parents c10da82 + 4ee0b8e
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diff --git a/docs/figures/lsu.pdf b/docs/figures/lsu.pdf
diff --git a/docs/figures/lsu.png b/docs/figures/lsu.png
diff --git a/docs/sections/load-store-unit.rst b/docs/sections/load-store-unit.rst
@@ -13,18 +13,18 @@ Queue (LDQ)**, and the **Store Queue (STQ)**. Load instructions generate a
 “uopLD" :term:`Micro-Op (UOP)`. When issued, "uopLD" calculates the load address and
 places its result in the LDQ. Store instructions (may) generate *two*
 :term:`UOP<Micro-Op (UOP)>` s, “uopSTA" (Store Address Generation) and “uopSTD" (Store Data
-Generation). The STA :term:`UOP<Micro-Op (UOP)>` calculates the store address and places its
-result in the SAQ queue. The STD :term:`UOP<Micro-Op (UOP)>` moves the store data from the
-register file to the SDQ. Each of these :term:`UOP<Micro-Op (UOP)>` s will issue out of the
+Generation). The STA :term:`UOP<Micro-Op (UOP)>` calculates the store address and updates the
+address in the STQ entry. The STD :term:`UOP<Micro-Op (UOP)>` moves the store data into the
+STQ entry. Each of these :term:`UOP<Micro-Op (UOP)>` s will issue out of the
 *Issue Window* as soon their operands are ready. See :ref:`Store Micro-Ops`
 for more details on the store :term:`UOP<Micro-Op (UOP)>` specifics.
 
 Store Instructions
 ------------------
 
 Entries in the Store Queue are allocated in the *Decode* stage (
-stq(i).valid is set). A “valid" bit denotes when an entry in the SAQ or
-SDQ holds a valid address or data (stq(i).bits.addr.valid and stq(i).bits.data.valid).
+stq(i).valid is set). A “valid" bit denotes when an entry in the STQ holds
+a valid address and valid data (stq(i).bits.addr.valid and stq(i).bits.data.valid).
 Once a store instruction is committed, the corresponding entry in the Store
 Queue is marked as committed. The store is then free to be fired to the
 memory system at its convenience. Stores are fired to the memory in program
@@ -45,7 +45,7 @@ on store-heavy code. Sequences involving stores to the stack should
 operate at IPC=1!
 
 However, it is common for store addresses to be known well in advance of
-the store data. Store addresses should be moved to the SAQ as soon as
+the store data. Store addresses should be moved to the STQ as soon as
 possible to allow later loads to avoid any memory ordering failures.
 Thus, the issue window will emit uopSTA or uopSTD :term:`UOP<Micro-Op (UOP)>` s as required,
 but retain the remaining half of the store until the second operand is