Revert "Do not connect the PTW if not usingPTW"

This reverts commit e9c3375.
riscv-boom · Mar 15, 2019 · 9e5a665 · 9e5a665
1 parent cf29dcf
commit 9e5a665
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Showing 2 changed files with 5 additions and 11 deletions.
diff --git a/src/main/scala/common/tile.scala b/src/main/scala/common/tile.scala
@@ -191,11 +191,7 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
   outer.dcache.module.io.hartid := constants.hartid
   dcachePorts += core.io.dmem // TODO outer.dcachePorts += () => module.core.io.dmem ??
   //fpuOpt foreach { fpu => core.io.fpu <> fpu.io } RocketFpu - not needed in boom
-  core.io.ptw := DontCare
-  if (usingPTW)
-  {
-    core.io.ptw <> ptw.io.dpath
-  }
+  core.io.ptw <> ptw.io.dpath
   core.io.rocc := DontCare
   core.io.fpu := DontCare
   core.io.reset_vector := DontCare
@@ -223,11 +219,8 @@ class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer)
   // TODO figure out how to move the below into their respective mix-ins
   dcacheArb.io.requestor <> dcachePorts
   ptwPorts += core.io.ptw_tlb
-  core.io.ptw_tlb := DontCare
-  if (usingPTW)
-  {
-    ptw.io.requestor <> ptwPorts
-  }
+  ptw.io.requestor <> ptwPorts
+
   val frontendStr = outer.frontend.module.toString
   ElaborationArtefacts.add(
     """core.config""",

diff --git a/src/main/scala/lsu/types.scala b/src/main/scala/lsu/types.scala
@@ -68,7 +68,8 @@ trait CanHaveBoomPTWModule extends HasBoomHellaCacheModule
 {
   val outer: CanHaveBoomPTW
   val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
-  val ptw = if (outer.usingPTW) Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) else null
+  val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
+  ptw.io <> DontCare // Is overridden below if PTW is connected
   if (outer.usingPTW)
   {
     dcachePorts += ptw.io.mem