Merge pull request #535 from sequencer/remove_deprecations

Remove deprecations for Chisel 3.5
riscv-boom · Apr 8, 2021 · add38db · add38db
2 parents 7892f79 + 7fd33b7
commit add38db
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Showing 4 changed files with 6 additions and 7 deletions.
diff --git a/src/main/scala/ifu/bpd/ras.scala b/src/main/scala/ifu/bpd/ras.scala
@@ -7,7 +7,6 @@ package boom.ifu
 
 import chisel3._
 import chisel3.util._
-import chisel3.core.{withReset}
 import chisel3.internal.sourceinfo.{SourceInfo}
 
 import freechips.rocketchip.config._

diff --git a/src/main/scala/ifu/bpd/sw_predictor.scala b/src/main/scala/ifu/bpd/sw_predictor.scala
@@ -20,10 +20,10 @@ class SwBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank(
     val pred_harness = Module(new BranchPredictorHarness)
 
     btb_harness.io.clock := clock
-    btb_harness.io.reset := reset.toBool
+    btb_harness.io.reset := reset.asBool
 
     pred_harness.io.clock := clock
-    pred_harness.io.reset := reset.toBool
+    pred_harness.io.reset := reset.asBool
 
 
     btb_harness.io.req_valid := s1_valid

diff --git a/src/main/scala/ifu/fetch-buffer.scala b/src/main/scala/ifu/fetch-buffer.scala
@@ -192,7 +192,7 @@ class FetchBuffer(implicit p: Parameters) extends BoomModule
   }
 
   // TODO Is this necessary?
-  when (reset.toBool) {
+  when (reset.asBool) {
     io.deq.bits.uops map { u => u.valid := false.B }
   }
 

diff --git a/src/main/scala/ifu/frontend.scala b/src/main/scala/ifu/frontend.scala
@@ -512,12 +512,12 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
   // **** F3 ****
   // --------------------------------------------------------
   val f3_clear = WireInit(false.B)
-  val f3 = withReset(reset.toBool || f3_clear) {
+  val f3 = withReset(reset.asBool || f3_clear) {
     Module(new Queue(new FrontendResp, 1, pipe=true, flow=false)) }
 
   // Queue up the bpd resp as well, incase f4 backpressures f3
   // This is "flow" because the response (enq) arrives in f3, not f2
-  val f3_bpd_resp = withReset(reset.toBool || f3_clear) {
+  val f3_bpd_resp = withReset(reset.asBool || f3_clear) {
     Module(new Queue(new BranchPredictionBundle, 1, pipe=true, flow=true)) }
 
 
@@ -855,7 +855,7 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
   // **** F4 ****
   // -------------------------------------------------------
   val f4_clear = WireInit(false.B)
-  val f4 = withReset(reset.toBool || f4_clear) {
+  val f4 = withReset(reset.asBool || f4_clear) {
     Module(new Queue(new FetchBundle, 1, pipe=true, flow=false))}
 
   val fb  = Module(new FetchBuffer)