Merge pull request #446 from riscv-boom/mem-ordering-overlap-fix

Check for mask overlap before flagging st->ld ordering failures
riscv-boom · Mar 5, 2020 · b3bf6d9 · b3bf6d9
2 parents a16e74a + 7b9c56e
commit b3bf6d9
Showing 1 changed file with 5 additions and 3 deletions.
diff --git a/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala
@@ -1040,7 +1040,8 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
 
     val block_addr_matches = widthMap(w => lcam_addr(w) >> blockOffBits === l_addr >> blockOffBits)
     val dword_addr_matches = widthMap(w => block_addr_matches(w) && lcam_addr(w)(blockOffBits-1,3) === l_addr(blockOffBits-1,3))
-    val mask_match = widthMap(w => (l_mask & lcam_mask(w)) === l_mask)
+    val mask_match   = widthMap(w => (l_mask & lcam_mask(w)) === l_mask)
+    val mask_overlap = widthMap(w => (l_mask & lcam_mask(w)).orR)
     val l_is_succeeding = succeeding_loads(i)
 
     // Searcher is a store
@@ -1058,7 +1059,8 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
                    ((l_bits.executed && !l_bits.execute_ignore && !executing_loads(i)) || l_bits.succeeded || l_is_succeeding) &&
                    !l_bits.addr_is_virtual                                                                                     &&
                    l_bits.st_dep_mask(lcam_stq_idx(w))                                                                         &&
-                   dword_addr_matches(w)) {
+                   dword_addr_matches(w)                                                                                       &&
+                   mask_overlap(w)) {
         val forwarded_is_older = IsOlder(l_bits.forward_stq_idx, lcam_stq_idx(w), l_bits.youngest_stq_idx)
         // We are older than this load, which overlapped us.
         when (!l_bits.forward_std_val || // If the load wasn't forwarded, it definitely failed
@@ -1075,7 +1077,7 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
                    l_bits.addr.valid          &&
                    !l_bits.addr_is_virtual    &&
                    dword_addr_matches(w)      &&
-                   ((lcam_mask(w) & l_mask) =/= 0.U)) {
+                   mask_overlap(w)) {
         val searcher_is_older = IsOlder(lcam_ldq_idx(w), i.U, ldq_head)
         when (searcher_is_older) {
           when (l_bits.executed        &&