Merge pull request #359 from riscv-boom/deprecate-3-stage-fetch

[ifu] Deprecate support for 3-cycle fetch pipeline
riscv-boom · Jul 27, 2019 · b530bfb · b530bfb
2 parents f9499c7 + 35176f6
commit b530bfb
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Showing 2 changed files with 5 additions and 8 deletions.
diff --git a/src/main/scala/common/parameters.scala b/src/main/scala/common/parameters.scala
@@ -181,7 +181,7 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
   val intToFpLatency = boomParams.intToFpLatency
 
   val fetchLatency = boomParams.fetchLatency // how many cycles does fetch occupy?
-  require (Seq(3, 4).contains(fetchLatency)) // 3 and 4 cycle fetch supported
+  require (fetchLatency == 4) // Only 4-cycle fetch is supported
   val renameLatency = boomParams.renameLatency // how many cycles does rename occupy?
 
   val enableBrResolutionRegister = boomParams.enableBrResolutionRegister

diff --git a/src/main/scala/ifu/fetch-control-unit.scala b/src/main/scala/ifu/fetch-control-unit.scala
@@ -136,7 +136,7 @@ class FetchControlUnit(implicit p: Parameters) extends BoomModule
   val r_f4_valid = RegInit(false.B)
 
   // Can the F3 stage proceed?
-  val f4_ready = ((!r_f4_valid && (fetchLatency == 4).B) || fb.io.enq.ready) && ftq.io.enq.ready
+  val f4_ready = (!r_f4_valid || fb.io.enq.ready) && ftq.io.enq.ready
 
   // F4 Redirection path.
   val r_f4_req = Reg(Valid(new PCReq()))
@@ -536,7 +536,7 @@ class FetchControlUnit(implicit p: Parameters) extends BoomModule
   } .otherwise {
     r_f4_req.valid := false.B
   }
-  r_f4_valid := r_f4_valid && !fb.io.enq.ready && !io.clear_fetchbuffer && (fetchLatency == 4).B || f3_fire
+  r_f4_valid := r_f4_valid && !fb.io.enq.ready && !io.clear_fetchbuffer || f3_fire
 
   assert (!(r_f4_req.valid && !r_f4_valid),
     "[fetch] f4-request is high but f4_valid is not.")
@@ -548,11 +548,8 @@ class FetchControlUnit(implicit p: Parameters) extends BoomModule
   //-------------------------------------------------------------
 
   // Fetch Buffer
-  if (fetchLatency == 3) fb.io.enq.valid := f3_fire && (f3_fetch_bundle.mask =/= 0.U)
-  else                   fb.io.enq.valid := r_f4_valid && (r_f4_fetch_bundle.mask =/= 0.U)
-
-  if (fetchLatency == 3) fb.io.enq.bits := f3_fetch_bundle
-  else                   fb.io.enq.bits := r_f4_fetch_bundle
+  fb.io.enq.valid := r_f4_valid && (r_f4_fetch_bundle.mask =/= 0.U)
+  fb.io.enq.bits := r_f4_fetch_bundle
   fb.io.clear := io.clear_fetchbuffer
 
   for (i <- 0 until fetchWidth) {