Decoupled load/store queue sizes.

src/main/scala/common/configs.scala

@@ -43,7 +43,8 @@ class DefaultBoomConfig extends Config((site, here, up) => {
             IssueParams(issueWidth=1, numEntries=20, iqType=IQT_FP.litValue)),
          numIntPhysRegisters = 100,
          numFpPhysRegisters = 64,
-         numLsuEntries = 16,
+         numLdqEntries = 32,
+         numStqEntries = 18,
          maxBrCount = 8,
          btb = BoomBTBParameters(nSets=512, nWays=4, nRAS=8, tagSz=13),
          enableBranchPredictor = true,
@@ -144,7 +145,8 @@ class WithSmallBooms extends Config((site, here, up) => {
             IssueParams(issueWidth=1, numEntries=4, iqType=IQT_FP.litValue)),
          numIntPhysRegisters = 48,
          numFpPhysRegisters = 48,
-         numLsuEntries = 8,
+         numLdqEntries=4,
+         numStqEntries=4,
          maxBrCount = 4,
          gshare = Some(GShareParameters(enabled=true, history_length=11, num_sets=2048)),
          nPerfCounters = 2),
@@ -169,7 +171,8 @@ class WithMediumBooms extends Config((site, here, up) => {
             IssueParams(issueWidth=1, numEntries=10, iqType=IQT_FP.litValue)),
          numIntPhysRegisters = 70,
          numFpPhysRegisters = 64,
-         numLsuEntries = 16,
+         numLdqEntries = 16,
+         numStqEntries = 9,
          maxBrCount = 8,
          regreadLatency = 1,
          renameLatency = 2,
@@ -199,7 +202,8 @@ class WithMegaBooms extends Config((site, here, up) => {
             IssueParams(issueWidth=1, numEntries=20, iqType=IQT_FP.litValue)),
          numIntPhysRegisters = 128,
          numFpPhysRegisters = 128,
-         numLsuEntries = 32,
+         numLdqEntries = 32,
+         numStqEntries = 18,
          maxBrCount = 16,
          btb = BoomBTBParameters(nSets=512, nWays=4, nRAS=16, tagSz=20),
          tage = Some(TageParameters())),

src/main/scala/common/micro-op.scala

@@ -87,8 +87,8 @@ class MicroOp(implicit p: Parameters) extends BoomBundle()(p)
                                                // then translate and sign-extend in execute
    val csr_addr         = UInt(CSR_ADDR_SZ.W)    // only used for critical path reasons in Exe
    val rob_idx          = UInt(ROB_ADDR_SZ.W)
-   val ldq_idx          = UInt(MEM_ADDR_SZ.W)
-   val stq_idx          = UInt(MEM_ADDR_SZ.W)
+   val ldq_idx          = UInt(LDQ_ADDR_SZ.W)
+   val stq_idx          = UInt(STQ_ADDR_SZ.W)
    val pdst             = UInt(PREG_SZ.W)
    val pop1             = UInt(PREG_SZ.W)
    val pop2             = UInt(PREG_SZ.W)

src/main/scala/common/parameters.scala

@@ -25,12 +25,13 @@ import boom.lsu._
 case class BoomCoreParams(
    fetchWidth: Int = 1,
    decodeWidth: Int = 1,
-   numRobEntries: Int = 16,
+   numRobEntries: Int = 64,
    issueParams: Seq[IssueParams] = Seq(
          IssueParams(issueWidth=1, numEntries=16, iqType=IQT_MEM.litValue),
          IssueParams(issueWidth=2, numEntries=16, iqType=IQT_INT.litValue),
          IssueParams(issueWidth=1, numEntries=16, iqType=IQT_FP.litValue)),
-   numLsuEntries: Int = 8,
+   numLdqEntries: Int = 16,
+   numStqEntries: Int = 16,
    numIntPhysRegisters: Int = 96,
    numFpPhysRegisters: Int = 64,
    enableCustomRf: Boolean = false,
@@ -114,14 +115,15 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
 
    //************************************
    // Data Structure Sizes
-   val NUM_ROB_ENTRIES  = boomParams.numRobEntries     // number of ROB entries (e.g., 32 entries for R10k)
-   val NUM_LSU_ENTRIES  = boomParams.numLsuEntries     // number of LD/ST entries
-   val MAX_BR_COUNT     = boomParams.maxBrCount        // number of branches we can speculate simultaneously
-   val ftqSz            = boomParams.ftq.nEntries
-   val fetchBufferSz    = boomParams.fetchBufferSz     // number of instructions that stored between fetch&decode
+   val NUM_ROB_ENTRIES = boomParams.numRobEntries       // number of ROB entries (e.g., 32 entries for R10k)
+   val NUM_LDQ_ENTRIES = boomParams.numLdqEntries       // number of LAQ entries
+   val NUM_STQ_ENTRIES = boomParams.numStqEntries       // number of SAQ/SDQ entries
+   val MAX_BR_COUNT    = boomParams.maxBrCount          // number of branches we can speculate simultaneously
+   val ftqSz           = NUM_ROB_ENTRIES / fetchWidth   // number of FTQ entries should match (or slightly exceed) ROB entries
+   val fetchBufferSz   = boomParams.fetchBufferSz       // number of instructions that stored between fetch&decode
 
-   val numIntPhysRegs   = boomParams.numIntPhysRegisters // size of the integer physical register file
-   val numFpPhysRegs    = boomParams.numFpPhysRegisters  // size of the floating point physical register file
+   val numIntPhysRegs  = boomParams.numIntPhysRegisters // size of the integer physical register file
+   val numFpPhysRegs   = boomParams.numFpPhysRegisters  // size of the floating point physical register file
 
    //************************************
    // Functional Units
@@ -240,10 +242,10 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
    val LREG_SZ           = log2Ceil(LOGICAL_REG_COUNT)
    val IPREG_SZ          = log2Ceil(numIntPhysRegs)
    val FPREG_SZ          = log2Ceil(numFpPhysRegs)
-   val PREG_SZ          = IPREG_SZ max FPREG_SZ
-   val MEM_ADDR_SZ       = log2Ceil(NUM_LSU_ENTRIES)
-   val MAX_ST_COUNT      = (1 << MEM_ADDR_SZ)
-   val MAX_LD_COUNT      = (1 << MEM_ADDR_SZ)
+   val PREG_SZ           = IPREG_SZ max FPREG_SZ
+   val LDQ_ADDR_SZ       = log2Ceil(NUM_LDQ_ENTRIES)
+   val STQ_ADDR_SZ       = log2Ceil(NUM_STQ_ENTRIES)
+   val LSU_ADDR_SZ       = LDQ_ADDR_SZ max STQ_ADDR_SZ
    val BR_TAG_SZ         = log2Ceil(MAX_BR_COUNT)
    val NUM_BROB_ENTRIES  = NUM_ROB_ROWS //TODO explore smaller BROBs
    val BROB_ADDR_SZ      = log2Ceil(NUM_BROB_ENTRIES)
@@ -253,8 +255,8 @@ trait HasBoomCoreParameters extends freechips.rocketchip.tile.HasCoreParameters
    require (MAX_BR_COUNT >=2)
    require (NUM_ROB_ROWS % 2 == 0)
    require (NUM_ROB_ENTRIES % decodeWidth == 0)
-   require (isPow2(NUM_LSU_ENTRIES))
-   require ((NUM_LSU_ENTRIES-1) > decodeWidth)
+   require ((NUM_LDQ_ENTRIES-1) > decodeWidth)
+   require ((NUM_STQ_ENTRIES-1) > decodeWidth)
 
    //************************************
    // Custom Logic

src/main/scala/exu/core.scala

@@ -386,7 +386,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
    + "\n   Issue Width           : " + issueParams.map(_.issueWidth).sum
    + "\n   ROB Size              : " + NUM_ROB_ENTRIES
    + "\n   Issue Window Size     : " + issueParams.map(_.numEntries) + iss_str
-   + "\n   Load/Store Unit Size  : " + NUM_LSU_ENTRIES + "/" + NUM_LSU_ENTRIES
+   + "\n   Load/Store Unit Size  : " + NUM_LDQ_ENTRIES + "/" + NUM_STQ_ENTRIES
    + "\n   Num Int Phys Registers: " + numIntPhysRegs
    + "\n   Num FP  Phys Registers: " + numFpPhysRegs
    + "\n   Max Branch Count      : " + MAX_BR_COUNT
@@ -581,8 +581,8 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
       dec_uops(w).ldq_idx := new_lidx
       dec_uops(w).stq_idx := new_sidx
 
-      new_lidx = Mux(dec_will_fire(w) && dec_uops(w).is_load,  WrapInc(new_lidx, NUM_LSU_ENTRIES), new_lidx)
-      new_sidx = Mux(dec_will_fire(w) && dec_uops(w).is_store, WrapInc(new_sidx, NUM_LSU_ENTRIES), new_sidx)
+      new_lidx = Mux(dec_will_fire(w) && dec_uops(w).is_load,  WrapInc(new_lidx, NUM_LDQ_ENTRIES), new_lidx)
+      new_sidx = Mux(dec_will_fire(w) && dec_uops(w).is_store, WrapInc(new_sidx, NUM_STQ_ENTRIES), new_sidx)
    }
 
    //-------------------------------------------------------------
@@ -1208,7 +1208,7 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg
 
       val numFtqWhitespace = if (DEBUG_PRINTF_FTQ) (ftqSz/4)+1 else 0
       val fetchWhitespace = if (fetchWidth >= 8) 2 else 0
-       var whitespace = (debugScreenheight - 25 + 3 -10 + 3 + 4 - decodeWidth - NUM_LSU_ENTRIES -
+       var whitespace = (debugScreenheight - 25 + 3 -10 + 3 + 4 - decodeWidth - (NUM_LDQ_ENTRIES max NUM_STQ_ENTRIES) -
          issueParams.map(_.numEntries).sum - issueParams.length - (NUM_ROB_ENTRIES/COMMIT_WIDTH) -
          numFtqWhitespace - fetchWhitespace
      )

src/main/scala/exu/execution-units/functional-unit.scala

@@ -179,8 +179,8 @@ class BrResolutionInfo(implicit p: Parameters) extends BoomBundle()(p)
    val pc_lob     = UInt(log2Ceil(fetchWidth*coreInstBytes).W)
    val ftq_idx    = UInt(ftqSz.W)
    val rob_idx    = UInt(ROB_ADDR_SZ.W)
-   val ldq_idx    = UInt(MEM_ADDR_SZ.W)  // track the "tail" of loads and stores, so we can
-   val stq_idx    = UInt(MEM_ADDR_SZ.W)  // quickly reset the LSU on a mispredict
+   val ldq_idx    = UInt(LDQ_ADDR_SZ.W)  // track the "tail" of loads and stores, so we can
+   val stq_idx    = UInt(STQ_ADDR_SZ.W)  // quickly reset the LSU on a mispredict
    val taken      = Bool()                     // which direction did the branch go?
    val is_jr      = Bool() // TODO remove use cfi_type instead
    val cfi_type   = CfiType()

src/main/scala/lsu/dcache-shim.scala

@@ -143,7 +143,7 @@ class DCacheReq(implicit p: Parameters) extends BoomBundle()(p)
 class NackInfo(implicit p: Parameters) extends BoomBundle()(p)
 {
    val valid      = Bool()
-   val lsu_idx    = UInt(MEM_ADDR_SZ.W)
+   val lsu_idx    = UInt(LSU_ADDR_SZ.W)
    val isload     = Bool()
    val cache_nack = Bool() // was the cache nacking us, or the LSU
                            // cache nacks for stuctural hazards (MUST kill st->ld forwardings)
@@ -206,8 +206,7 @@ class DCMemPortIO(implicit p: Parameters) extends BoomBundle()(p)
 class DCacheShim(implicit p: Parameters) extends BoomModule()(p)
    with freechips.rocketchip.rocket.constants.MemoryOpConstants
 {
-   val max_num_inflight = MAX_LD_COUNT
-   isPow2(max_num_inflight)
+   val max_num_inflight = NUM_LDQ_ENTRIES
 
    val io = IO(new Bundle
    {