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[lsu] when VM is disabled pass firrtl build
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abejgonzalez committed Feb 5, 2019
1 parent 3b27889 commit da222a9
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1 change: 1 addition & 0 deletions src/main/scala/lsu/types.scala
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ trait CanHaveBoomPTWModule extends HasBoomHellaCacheModule {
val outer: CanHaveBoomPTW
val ptwPorts = ListBuffer(outer.dcache.module.io.ptw)
val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p))
ptw.io <> DontCare // Is overridden below if PTW is connected
if (outer.usingPTW) {
dcachePorts += ptw.io.mem
}
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