Merge pull request #463 from riscv-boom/counters

[core] Add basic cache counters

src/main/scala/exu/core.scala

@@ -260,11 +260,11 @@ class BoomCore(implicit p: Parameters) extends BoomModule
     )),
 
     new freechips.rocketchip.rocket.EventSet((mask, hits) => (mask & hits).orR, Seq(
-//      ("I$ miss",     () => io.ifu.perf.acquire),
-//      ("D$ miss",     () => io.dmem.perf.acquire),
-//      ("D$ release",  () => io.dmem.perf.release),
-//      ("ITLB miss",   () => io.ifu.perf.tlbMiss),
-//      ("DTLB miss",   () => io.dmem.perf.tlbMiss),
+      ("I$ miss",     () => io.ifu.perf.acquire),
+      ("D$ miss",     () => io.lsu.perf.acquire),
+      ("D$ release",  () => io.lsu.perf.release),
+      ("ITLB miss",   () => io.ifu.perf.tlbMiss),
+      ("DTLB miss",   () => io.lsu.perf.tlbMiss),
       ("L2 TLB miss", () => io.ptw.perf.l2miss)))))
   val csr = Module(new freechips.rocketchip.rocket.CSRFile(perfEvents, boomParams.customCSRs.decls))
   csr.io.inst foreach { c => c := DontCare }

src/main/scala/ifu/frontend.scala

@@ -283,6 +283,8 @@ class BoomFrontendIO(implicit p: Parameters) extends BoomBundle
   val commit = Valid(UInt(ftqSz.W))
 
   val flush_icache = Output(Bool())
+
+  val perf = Input(new FrontendPerfEvents)
 }
 
 /**
@@ -334,6 +336,8 @@ class BoomFrontendModule(outer: BoomFrontend) extends LazyModuleImp(outer)
   icache.io.invalidate := io.cpu.flush_icache
   val tlb = Module(new TLB(true, log2Ceil(fetchBytes), TLBConfig(nTLBEntries)))
   io.ptw <> tlb.io.ptw
+  io.cpu.perf.tlbMiss := io.ptw.req.fire()
+  io.cpu.perf.acquire := icache.io.perf.acquire
 
   // --------------------------------------------------------
   // **** NextPC Select (F0) ****

src/main/scala/ifu/icache.scala

@@ -102,6 +102,10 @@ class ICacheBundle(val outer: ICache) extends BoomBundle()(outer.p)
 
   val resp = Valid(new ICacheResp(outer))
   val invalidate = Input(Bool())
+
+  val perf = Output(new Bundle {
+    val acquire = Bool()
+  })
 }
 
 /**
@@ -352,6 +356,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   tl_out.c.valid := false.B
   tl_out.e.valid := false.B
 
+  io.perf.acquire := tl_out.a.fire()
+
   when (!refill_valid) { invalidated := false.B }
   when (refill_fire) { refill_valid := true.B }
   when (refill_done) { refill_valid := false.B }

src/main/scala/lsu/dcache.scala

@@ -810,6 +810,9 @@ class BoomNonBlockingDCacheModule(outer: BoomNonBlockingDCache) extends LazyModu
   io.lsu.release.valid := wb.io.lsu_release.valid || prober.io.lsu_release.valid
   TLArbiter.lowest(edge, tl_out.c, wb.io.release, prober.io.rep)
 
+  io.lsu.perf.release := edge.done(tl_out.c)
+  io.lsu.perf.acquire := edge.done(tl_out.a)
+
   // load data gen
   val s2_data_word_prebypass = widthMap(w => s2_data_muxed(w) >> Cat(s2_word_idx(w), 0.U(log2Ceil(coreDataBits).W)))
   val s2_data_word = Wire(Vec(memWidth, UInt()))

src/main/scala/lsu/lsu.scala

@@ -101,6 +101,11 @@ class LSUDMemIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)
   val force_order  = Output(Bool())
   val ordered     = Input(Bool())
 
+  val perf = Input(new Bundle {
+    val acquire = Bool()
+    val release = Bool()
+  })
+
   override def cloneType = new LSUDMemIO().asInstanceOf[this.type]
 }
 
@@ -145,6 +150,12 @@ class LSUCoreIO(implicit p: Parameters) extends BoomBundle()(p)
   val lxcpt       = Output(Valid(new Exception))
 
   val tsc_reg     = Input(UInt())
+
+  val perf        = Output(new Bundle {
+    val acquire = Bool()
+    val release = Bool()
+    val tlbMiss = Bool()
+  })
 }
 
 class LSUIO(implicit p: Parameters, edge: TLEdgeOut) extends BoomBundle()(p)
@@ -239,6 +250,9 @@ class LSU(implicit p: Parameters, edge: TLEdgeOut) extends BoomModule()(p)
     instruction = false, lgMaxSize = log2Ceil(coreDataBytes), rocket.TLBConfig(dcacheParams.nTLBEntries)))
 
   io.ptw <> dtlb.io.ptw
+  io.core.perf.tlbMiss := io.ptw.req.fire()
+  io.core.perf.acquire := io.dmem.perf.acquire
+  io.core.perf.release := io.dmem.perf.release
 
 
   val clear_store     = WireInit(false.B)