Verilog codes of Boom

[Shalaleh]

Hello,
I am totally new to riscv-boom. and I need verilog codes of boom.
I did everything at where in the Readme file. Could someone please help me how I can get the Verilog codes of Boom?

Thanks in advance

[jerryz123]

Running make in boom-template/verisim will put the generated verilog in boom-template/verisim/generated-src

[Shalaleh]

Thank you.
and if I want to generate Bitstream via Vivado for Riscv-Boom to be implemented on Zedboard, How can I create Constraint file?

Thanks in advance

[abejgonzalez]

Hi @Shalaleh, has this already been resolved on your end? If so, I will go ahead and close this issue.

[Shalaleh]

Hello, No, I gave up at the end.

…

On Tue, 28 May 2019 at 02:37, Abraham Gonzalez ***@***.***> wrote: Hi @Shalaleh <https://github.com/Shalaleh>, has this already been resolved on your end? If so, I will go ahead and close this issue. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#125?email_source=notifications&email_token=AKQX77FLSA3YMQSXBZK6Y2DPXR5DJA5CNFSM4GBY2DTKYY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGODWKVQPQ#issuecomment-496326718>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AKQX77GPQKMCEVPUUCM5R4TPXR5DJANCNFSM4GBY2DTA> .

-- Shalaleh Samadi M. Sc. in Mathematics

[abejgonzalez]

Sorry to hear that. More recently this was released on our end: https://github.com/riscv-boom/fpga-zynq. It might help answer some of your questions. Good luck with future hacking.