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muti-core-boom-simutor can run multi-thread coremark? #528
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How are you running compiling and running multithreaded coremark? In general SonicBOOM supports multithreaded applications. |
1. my method to compile multithread coremark 2. my method to run multithread coremark |
I don't believe pk supports pthreads. What does |
my info returned is as below:
I have a question. When using spike, spike provide simulation env? In your cmd, no boom simulator is specified. |
Spike is the RISC-V functional ISA simulator. |
So what should I do to run multithreaded coremark? In general, how can we run multithreaded applications with simulator-chipyard-SmallBoomConfig-debug? Do you have any suggestions?Thanks! |
You have to compile coremark in baremetal mode (no pk), and then edit the baremetal initialization code to boot up all harts. https://github.com/riscv-boom/riscv-coremark/tree/master/riscv64-baremetal contains files for compiling coremark in baremetal. That repo also contains a script to do this. |
I'm sorry to bother you. After generating coremark.bare.riscv which has modified crt.S, what method should I do to run this coremark. Previously, using cmd "boom_simulator pk coremark.riscv 0x0 0x0 0x66 1", the riscv application can be run. But without pk, how can I run the riscv application? |
You can just run directly |
As you pointed, spike is a RISCV-V functional ISA simulator, not real boom simulator. So, Whether is there a method to run multi-thread application in boom's multi-core simulator? I want to see the coremark difference between single-thread on single boom core and multi-threads on multi boom cores. |
If a binary can be executed with |
I have tried to run coremark.bare.riscv on spike with cmd "spike coremark.bare.riscv". No error occurs but "Total time" and "Iterations/Sec" can not be printed. Cmd log is as follow:
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Hi guys, |
Can you post, or email to me, a waveform from this run? |
Hi,
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I also upload the riscv and objdump files of 1-thread-with-lpthread and 1-thread-without-lpthread coremark. You can download all these files from my repository, "https://github.com/qqjinger/fileShare". |
Can you verify this binary works on a dual-core rocket design first? It looks like there is something wrong with the binary ELF that is causing the binary loader to attempt to write to a non-existent memory address (0x7fff_f000) |
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Hi, |
I have a same problem when I run coremark.bare.riscv on the boom. I just run the normal coremark for 1 iteration. And I get the log with no Total time and Iteration/Sec
May be I think it has the same problem as bellow. Has the author of this issue solved the problem?
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Hi,
I have generated a SmallBoomConfig-debug with 2 cores configuration.At the same time, 1-thread coremark.riscv and 2-thread coremark.riscv are generated.
1-thread coremark.riscv can be run correctly on simulator SmallBoomConfig-debug and get right coremark. However, when 2-thread coremark.riscv run on SmallBoomConfig-debug , a error occurs, whose pc=fffffffffffffffe. Obviously, pc is out of control. So whether sonicboom does support run multi-thread riscv program? Or should I modify boom code somewhere?
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