Beagle QoR Changes #330

bkorpan · 2019-07-12T19:05:35Z

Type of change: other enhancement

Impact: rtl refactoring

Development Phase: implementation

Release Notes
Experimental QoR changes for BEAGLE.

…only updating upon mispredicts.

… in BrResolutionInfo.

…een.

…ompressed or straddling the fetch bundle edge.

… the index, as this tends to be a source of 'unfortunate coincidences' w.r.t. hashing collisions when training a loop.

…dictor is redirecting. This seems fairly common.

…anning to redirect the next cycle.

…ecessary.

…d micro-ops in the ren2 stage.

… jalr needs to be computed at XLEN width and then encoded as a vaddr.

…ave folding of the edge_inst offset.

bkorpan added 30 commits July 12, 2019 11:02

[gshare] Only update counter table on mispredicts.

f91aba3

[gshare] Use a counter update function which uses all 4 states while …

15fb34d

…only updating upon mispredicts.

[config] Fixed SmallBoomConfig FTQ sizing.

10de7b4

[config] Specify a btb for SmallBoomConfig.

bd1c284

[microop] Added cfi_idx field to MicroOp.

b074703

[exu] Replaced pc_lob field and getCfiIdx function with cfi_idx field…

2c54a86

… in BrResolutionInfo.

[ifu] Don't perform an F3 (F4) btb update unless F4 is valid.

154f590

[gshare] Do indexing on the granularity of ICache banks.

ea37ced

[bpu] Reenabled RAS. Only pushes calls onto the stack in F3 for now.

74f71e3

[branch-checker] Fixed return address calculation.

11efe9f

[btb] Remember if a branch was compressed.

3654f34

[bpu] Let the BTB push calls onto the RAS.

9bd4dec

[ifu] Only perform an F3 BTB update when an earlier jr has not been s…

6c47665

…een.

[btb] Have the BTB track whether its CFI was an edge instruction.

32e9773

[ifu] Make sure BTB updates done by the BPD indicate if the CFI was c…

d75353a

…ompressed or straddling the fetch bundle edge.

[gshare] Added GShareEntry bundle.

b44cae2

[gshare] Added getUpdated function to GShareEntry.

6c7eddf

[gshare] Added getTakens function to GShareEntry.

3b202ee

[gshare] Updated logic from old row system to new entry system.

082d2db

[gshare] Updated index hash.

8124172

[gshare] Reenabled counter strengthening updates.

ee51077

[bpu] Tweaked path history function.

9957e0b

[bpu] Fixed history update.

797cbfa

[gshare] Improved index hash.

93d39d2

[gshare] Don't hash the PC low order bits into the high order bits of…

f80f6ea

… the index, as this tends to be a source of 'unfortunate coincidences' w.r.t. hashing collisions when training a loop.

[ras] Prevent the ras from performing an update while the backing pre…

c62156e

…dictor is redirecting. This seems fairly common.

[ras] Also prevent btb-based updates when the backing predictor is pl…

4e92429

…anning to redirect the next cycle.

[fetchmonitor] Fixed assert typo.

3641e70

[btb-sa] Modified index hash to improve utilization.

1749f3e

[bpd] Remove bankBytes parameter from bpd/gshare as it is no longer n…

749ac45

…ecessary.

bkorpan added 28 commits July 12, 2019 11:02

[ifu] Simplified f3_bundle_mask generation.

f8418a1

[ifu] Only do a BTB update if r_f4_req is valid.

f2ab3e3

Added MapReq and RemapReq bundles to MapTable.

f72c75f

Simplified RenameMaptable interface.

79d34fd

Delayed dispatch into ROB/LSU/RoCC by a cycle into the ren2 stage.

be4434a

Make sure uops in ren2 are rolled back.

e50a000

Make sure decode can't fire during rollback.

2bfbea9

Make sure the physical register leak detector takes into account vali…

966c7f3

…d micro-ops in the ren2 stage.

Simplified Freelist interface.

4b8e9d5

Style tweaks.

a351ce6

Make sure sfence flushes also unwind ren2.

e98990d

Reshift RoCC allocation to dispatch stage.

93bedce

Properly enforce limit of one RoCC dispatch per cycle.

e1fee7d

[bru] Tweaked PC and next PC generation logic.

52b9e2f

[bru] Naming tweaks.

c6810eb

[alu] Use uop in lieu of io.req.bits.uop.

b863569

[bru] Split off datapaths for computing jalr and jal/br targets. Only…

a95fc15

… jalr needs to be computed at XLEN width and then encoded as a vaddr.

[alu] Remove unecessary arithmetic preceeding ALU input.

6fbed0c

[bru] Cleanup target calculation and make it more amenable to carry-s…

27c6f34

…ave folding of the edge_inst offset.

[bru] Fix naming mistake.

f046158

[bru] Use SInt for target calculation.

aeafc34

[bru] Don't forget to cast back to UInt.

d711612

[bru] Don't try to avoid duplication of PC gen logic.

692a0e4

[bru] Make sure edge_inst offset doesn't get sign extended incorrectly.

d6606c0

[bru] Can't avoid edge instruction adjustment on PC input to ALU.

11ea33d

[ifu] Deassert prev_is_half upon fetchbuffer flush.

1ecc9b8

[ifu] Remove unnecessary comparison with PC.

16d94c6

[lsu] Delay execution of uncacheable loads by a cycle.

d7f71ef

abejgonzalez merged commit 0c0288e into beagle-boom Jul 12, 2019

bkorpan deleted the beagle-qor-changes branch July 25, 2019 17:37

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Beagle QoR Changes #330

Beagle QoR Changes #330

bkorpan commented Jul 12, 2019

Beagle QoR Changes #330

Beagle QoR Changes #330

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bkorpan commented Jul 12, 2019