[ren] Separate INT/FP Rename Instantiations #347
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jerryz123
reviewed
Jul 22, 2019
| /** | ||
| * TODO This is a bit nasty, but it's currently necessary to | ||
| * split the INT/FP rename pipelines into separate instantiations. | ||
| * Won't have to do this anymore with a properly decoupled FP pipeline. |
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How do you plan on handling int-to-fp/fp-to-int moves without doing this ugly merge step?
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If the FP rename pipeline ends up living behind a queue, fp-to-int could be handled the same as it is now. int-to-fp would need to use some sort of structure to match up fp destinations to the uops coming from the int side.
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This boots fedora. |
jerryz123
reviewed
Jul 28, 2019
| @@ -104,7 +104,11 @@ class BoomCore(implicit p: Parameters, edge: freechips.rocketchip.tilelink.TLEdg | |||
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| val decode_units = for (w <- 0 until decodeWidth) yield { val d = Module(new DecodeUnit); d } | |||
| val dec_brmask_logic = Module(new BranchMaskGenerationLogic(coreWidth)) | |||
| val rename_stage = Module(new RenameStage(coreWidth, numIntRenameWakeupPorts, numFpWakeupPorts)) | |||
| val rename_stage = Module(new RenameStage(coreWidth, numIntPhysRegs, numIntRenameWakeupPorts, false)) | |||
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Nit, but naming this int_rename_stage might make more sense,
Although if FP-pipeline becomes more decoupled, this naming is fine,
jerryz123
approved these changes
Jul 28, 2019
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This needs rebasing for a very simple merge conflict. |
…es based on rtypes.
jerryz123
added a commit
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Mar 11, 2021
* Refactor how Configs parameterize the Top and TestHarnesses * Bump sha3, testchipip, icenet, firesim
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Type of change: other enhancement
Impact: rtl refactoring
Development Phase: implementation
Release Notes
Describe the INT/FP pipelines as separate instantiations of a module, rather than a single instantiation.