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RISC-V: Support vundefine intrinsics for tuple types
riscv-non-isa/rvv-intrinsic-doc#288 gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (vundefined): Add vundefine intrinsics for tuple types. * config/riscv/riscv-vector-builtins.cc: Ditto. * config/riscv/vector.md (@vundefined<mode>): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/tuple_vundefined.c: New test.
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73
gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c
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/* { dg-do compile } */ | ||
/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */ | ||
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#include "riscv_vector.h" | ||
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vfloat16mf4x2_t | ||
test_vundefined_f16mf4x2 () | ||
{ | ||
return __riscv_vundefined_f16mf4x2 (); | ||
} | ||
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vfloat32m1x3_t | ||
test_vundefined_f32m1x3 () | ||
{ | ||
return __riscv_vundefined_f32m1x3 (); | ||
} | ||
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vfloat64m1x5_t | ||
test_vundefined_f64m1x5 () | ||
{ | ||
return __riscv_vundefined_f64m1x5 (); | ||
} | ||
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vint8mf4x2_t | ||
test_vundefined_i8mf4x2 () | ||
{ | ||
return __riscv_vundefined_i8mf4x2 (); | ||
} | ||
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vint16mf4x8_t | ||
test_vundefined_i16mf4x8 () | ||
{ | ||
return __riscv_vundefined_i16mf4x8 (); | ||
} | ||
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vint32m1x7_t | ||
test_vundefined_i32m1x7 () | ||
{ | ||
return __riscv_vundefined_i32m1x7 (); | ||
} | ||
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vint64m1x4_t | ||
test_vundefined_i64m1x4 () | ||
{ | ||
return __riscv_vundefined_i64m1x4 (); | ||
} | ||
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vuint8mf8x2_t | ||
test_vundefined_u8mf8x2 () | ||
{ | ||
return __riscv_vundefined_u8mf8x2 (); | ||
} | ||
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vuint16mf4x4_t | ||
test_vundefined_u16mf4x4 () | ||
{ | ||
return __riscv_vundefined_u16mf4x4 (); | ||
} | ||
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vuint32m1x7_t | ||
test_vundefined_u32m1x7 () | ||
{ | ||
return __riscv_vundefined_u32m1x7 (); | ||
} | ||
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vuint64m4x2_t | ||
test_vundefined_u64m4x2 () | ||
{ | ||
return __riscv_vundefined_u64m4x2 (); | ||
} | ||
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/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 18 } } */ | ||
/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */ |