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sbi_trap_error: hart2: trap handler failed (error -5) #65
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Do you have the U-Boot SMP patches included ? Refer: https://github.com/riscv/opensbi/blob/master/docs/platform/sifive_fu540.md |
Yes, of course. |
I'm also often seeing trap errors while opensbi is still booting. sbi_trap_error: hart1: misaligned store handler failed (error -10) OpenSBI v0.1 (Feb 14 2019 12:10:27) / __ \ / | _ _ | sbi_trap_error: hart1: mepc=0x80005bae mstatus=0xa00001800 sbi_trap_error: hart1: s2=0x2 s3=0x8000b018 |
That's strange. Me and Atish don't see this issue. Can you try pre-built riscv64 toolchain from bootlin at Some of us use this toolchain for cross-compilation. |
I'm not cross compiling. You can try out the packages from https://download.opensuse.org/ports/riscv/tumbleweed/repo/oss/. |
Do you have steps for setting-up SUSE RISC-V rootfs with native compiler?? We can try at our end. |
There are rootfs tarballs available in https://download.opensuse.org/ports/riscv/tumbleweed/images. The JeOS-devel image has a compiler pre-installed. |
I tried from fedora rootfs. I did not see any issue. I will try opensuse one tomorrow and report. |
I did not see any issue with native toolchain on OpenSUSE. This is what I did.
Can you please try with the above rootfs or gcc toolchain and master OpenSBI ? |
Did you use the reset button on the HiFive Unleashed board to reset the system? I am also seeing some other strange behavior when using the reset button. Quite often, OpenSBI will pass an unmodified device tree to the payload. Without the Linux SMP patches, this cause the kernel boot to hang as it waits for hart 0 to come up. |
With a warm reset it often hangs inside opensbi. That looks like something is using uninitialized memory. |
sbi_trap_error: hart3: trap handler failed (error -5) mepc=0x0000000080003e58 is at load_u8 in sbi_misaligned_load_handler. Shouldn't the trap handler first verify that the address is actually valid? |
If the same kernel (modulo built-in initrd) is booted via bbl the issue does not occur. |
@lukasauer : Yes I am able to reproduce your use case with reset button. I have always used external power reset instead of reset button. That's why I never saw this issue. This is what I am seeing.
I am looking into this. |
@andreas-schwab : Do you also see all the issues only when reset button is used ? |
The initial issue also happens after a cold boot. |
@andreas-schwab I tried OpenSuse toolchain and I couldn't reproduce the issue with cold boot. I am looking into the warm boot issue. |
Try running git fetch over NFS. |
@andreas-schwab @lukasauer : Can you please try the PR #84 on top of master ? Please save the objdump of openSBI in case you still see the exception. |
Doesn't change anything. |
Well it changed for us. We are not able to reproduce the issue our end at least with the master branch. SiFive folks also suggested that reset button on HiFive Unleashed has some issues and known to behave unexpectedly sometimes. It is better to use the power reset button (which just works) if warm reset button still showcase problems that we don't see. |
This issue has nothing to do with resetting. |
sbi_trap_error: hart2: trap handler failed (error -5) |
Looks good. |
No, it is still broken. sbi_trap_error: hart4: trap handler failed (error -5) |
sbi_trap_error: hart4: trap handler failed (error -5)
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#include <sys/mman.h> int |
Thanks for the traces. It makes sense now. I will soon send a patch fix to handle this case. |
Andreas, I tried your test code on QEMU but was not able to reproduce the issue so could you try my latest patches at your end. My latest patches are in mprv_trap_v2 branch of https://github.com/avpatel/opensbi.git Regards, |
Looks good so far. |
Thanks, I will wait 1 more day before merging this patch. Meanwhile, can you provide Tested-by to my patches on OpenSBI. Regards, |
All required changes are merged in riscv/opensbi. I am assuming you are not seeing this issue anymore. If you see this issue again then please re-open. Regards, |
sbi_trap_error: hart2: trap handler failed (error -5)
sbi_trap_error: hart2: mcause=0xd mtval=0x155574e000
sbi_trap_error: hart2: mepc=0x80003dba mstatus=0x8000000a00027822
sbi_trap_error: hart2: ra=0x80001eaa sp=0x80011d60
sbi_trap_error: hart2: gp=0x2aaaccdd18 tp=0x155573cb30
sbi_trap_error: hart2: s0=0x80011dc0 s1=0x5e
sbi_trap_error: hart2: a0=0x20000 a1=0x80011df0
sbi_trap_error: hart2: a2=0x15555eee96 a3=0x8000000a00006022
sbi_trap_error: hart2: a4=0x80011d6b a5=0x155574e001
sbi_trap_error: hart2: a6=0x0 a7=0x155574e001
sbi_trap_error: hart2: s2=0xee s3=0x3
sbi_trap_error: hart2: s4=0x96 s5=0x20
sbi_trap_error: hart2: s6=0x0 s7=0x15555eee96
sbi_trap_error: hart2: s8=0x74 s9=0x14774
sbi_trap_error: hart2: s10=0x58782b5b s11=0x34fe3e52
sbi_trap_error: hart2: t0=0x4 t1=0x155574dffd
sbi_trap_error: hart2: t2=0x55 t3=0x85a303
sbi_trap_error: hart2: t4=0x0 t5=0x0
sbi_trap_error: hart2: t6=0x15
The kernel was booted via u-boot.
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