RISC-V BFloat 16 extensions standardisation work.
This repository is used to develop standardisation proposals for Bfloat16 (Brain Float 16) instruction set extensions for the RISC-V architecture.
// I don't think this Task Group has a wiki page (or I could not find it) // For a general overview of the extension status and ratification progress, // please see // our page on the RISC-V Wiki.
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Note: See the main branch for the most up to date version.
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Note: These instructions are a work in progress. Their specifications will to change before being accepted as part of the RISC-V standard. While there are experimental encodings assigned to the proposed instructions, they should not be depended upon. They only exist to enable a toolchain and simulator flow. They will change.
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See the project board for a list of on-going / open issues. "How Can I Help?"
To see the latest draft release of the proposals, look at the Releases tab of the Github Repository.
Source code and supplementary information is found in the doc/ directory.
