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ld: can't relax section: Success #205

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cliffordwolf opened this issue Dec 10, 2016 · 5 comments
Closed

ld: can't relax section: Success #205

cliffordwolf opened this issue Dec 10, 2016 · 5 comments

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@cliffordwolf
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I've derived the following test case from the gcc -E output for auipc.S from riscv-tests:

.text
.global main
main:
addi a0,zero,0
addi a1,zero,0
jal zero,main
.ascii "mytest"
.align 3

With 805ee1d (built with --with-arch=RV32I) I get the following error:

$ /opt/riscv32i/bin/riscv32-unknown-elf-gcc test.S
/opt/riscv32i/lib/gcc/riscv32-unknown-elf/6.1.0/../../../../riscv32-unknown-elf/bin/ld: can't relax section: Success
collect2: error: ld returned 1 exit status

The test case is minimal in the sense that commenting out any of the three instructions, the .ascii statement, or the .align statement makes the problem disappear.

@cliffordwolf
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Can you guys reproduce this? Is anyone working on it? Is there anything I can do to help?

After updating to e3e50c5 (and changing the configure parameter --with-arch=RV32I to --with-arch=rv32i to fix the build) I still get the same can't relax section: Success error for my test.S file.

I'm currently not updating riscv-gnu-toolchain for PicoRV32 because of this problem.

@sorear
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sorear commented Dec 15, 2016

@palmer-dabbelt Do any of your recent relocation fixes impact this test?

@aswaterman
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I'll look into it

@aswaterman
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The problem manifests because the text section lost word alignment. Currently, .align on text sections only does the right thing if the text section is already 4-byte aligned (or 2-byte aligned for RVC). You can work around this by putting the string in the data section.

Working on a fix...

aswaterman added a commit to riscvarchive/riscv-binutils-gdb that referenced this issue Dec 16, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205
@aswaterman
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Should be fixed in riscv-binutils-gdb. Re-running test suite, then we can push to riscv-gnu-toolchain.

aswaterman added a commit to riscvarchive/riscv-binutils-gdb that referenced this issue Dec 19, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205
palmer-dabbelt pushed a commit to riscvarchive/riscv-binutils-gdb that referenced this issue Dec 20, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205

gas/ChangeLog

2016-12-16 Andrew Waterman <andrew@sifive.com>

        * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
        * config/tc-riscv.c (riscv_frag_align_code): New variable
        min_text_alignment_order, to pass to frag_align_code.
aswaterman added a commit to riscvarchive/riscv-binutils-gdb that referenced this issue Dec 20, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205

gas/ChangeLog

2016-12-16 Andrew Waterman <andrew@sifive.com>

        * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
        * config/tc-riscv.c (riscv_frag_align_code): New variable
        min_text_alignment_order, to pass to frag_align_code.
wallento pushed a commit to wallento/binutils-gdb that referenced this issue Dec 21, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205

	* config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
	(riscv_frag_align_code): Correct frag_align_code arg.
palmer-dabbelt pushed a commit to riscvarchive/riscv-binutils-gdb that referenced this issue Dec 21, 2016
Previously, the alignment directives were not correctly supported
in the text section when current alignment was only 1 byte (i.e.,
when the address was odd).  Since there are no 1-byte instructions
in RISC-V, this patch resolves the bug by writing a zero byte to
obtain 2-byte alignment, at which point a 2-byte NOP can be used
to obtain 4-byte alignment.

Resolves riscv-collab/riscv-gnu-toolchain#205

gas/ChangeLog

2016-12-16 Andrew Waterman <andrew@sifive.com>

        * config/tc-riscv.c (riscv_make_nops): Emit 2-byte NOPs.
        * config/tc-riscv.c (riscv_frag_align_code): New variable
        min_text_alignment_order, to pass to frag_align_code.
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