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@ucb-bar @riscv @sifive @freechipsproject @chipsalliance
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Popular repositories

  1. Original RISC-V 1.0 implementation. Not supported.

    Verilog 23 13

  2. Forked from chipsalliance/rocket-chip

    Rocket Chip Generator

    Scala

1,365 contributions in the last year

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Mon Wed Fri

Contribution activity

January 2022

Created a pull request in riscv/riscv-isa-manual that received 11 comments

Add Zihintntl spec

Non-temporal locality hints. See text.

+204 −0 11 comments
Opened 3 other pull requests in 3 repositories
riscv/riscv-profiles 1 merged
riscv-non-isa/riscv-elf-psabi-doc 1 closed
riscv-software-src/riscv-isa-sim 1 merged
Reviewed 6 pull requests in 5 repositories
riscv-software-src/riscv-isa-sim 2 pull requests
chipsalliance/chisel3 1 pull request
riscv/riscv-isa-manual 1 pull request
riscv/riscv-profiles 1 pull request
chipsalliance/rocket-chip 1 pull request
34 contributions in private repositories Jan 2 – Jan 19

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