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Without HTIF: 5000 instructions executed, then spike hangs #54

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neuschaefer opened this issue Jun 17, 2016 · 1 comment
Open

Without HTIF: 5000 instructions executed, then spike hangs #54

neuschaefer opened this issue Jun 17, 2016 · 1 comment

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@neuschaefer
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Hi, I encountered this problem while debugging coreboot, which doesn't use the HTIF.

If a program doesn't provide the tohost ELF symbol, spike will execute 5000 instructions and then hang in a loop without executing any more instructions. I tested this with spike f5ecf65 and riscvarchive/riscv-fesvr@916191caf3.

One easy way to proproduce this bug is to:

  • Write a program that spins a loop
  • run spike -l pk ./program to verify that execution doesn't stop
  • copy pk into the current directory
  • find the tohost string in pk and patch it to something else (like nohost)
  • run spike -l ./pk ./program |& tee trace-log; observe that execution stops at some point
  • run wc -l trace-log and observe that 5000 instructions have been executed

I haven't fully debugged it, but I've seen the following happening:

  • sim_t::run() calls step(INTERLEAVE), INTERLEAVE is defined as 5000
  • sim_t::step(n) simulates n instrucions, does some bookkeeping and finally calls htif->tick()
  • htif_isasim_t::tick() calls tick_once()
  • tick_once() calls htif_pthread_t::recv which calls recv_nonblocking
  • recv_nonblocking doesn't find any data, so it calls host.switch_to()
  • the other thread (this is some kind of cooperative multitasking, right?) doesn't switch back, because it's stuck in the loop in htif_t::run()

It might not be related to this problem, but I noticed that both spike and libfesvr register their own handlers for SIGINT. As signal handlers don't automatically stack, this is probably a bad idea.

@aswaterman
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We'll deal with most of this when we get rid of the HTIF, very soon.

The SIGINT handler thing is probably benign, but is nevertheless a design flaw.

pgeorgi pushed a commit to coreboot/coreboot that referenced this issue Jul 14, 2016
See riscv-software-src/riscv-isa-sim#54 for more
information.

Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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