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Fixes floating point register names, Removes floating point load, sto…
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…re and move, Fixes handling of MISA and clear the code a bit
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@abukharmeh
abukharmeh committed Dec 21, 2020
1 parent b28bfc2 commit 2d0c506
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Showing 6 changed files with 214 additions and 180 deletions.
1 change: 1 addition & 0 deletions c_emulator/riscv_sail.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@ void zrvfi_get_exec_packet(sail_bits *rop, unit);
#endif

extern mach_bits zxlen_val;
extern int64_t zzzfinx_en;
extern bool zhtif_done;
extern mach_bits zhtif_exit_code;
extern bool have_exception;
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1 change: 1 addition & 0 deletions c_emulator/riscv_sim.c
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Original file line number Diff line number Diff line change
Expand Up @@ -307,6 +307,7 @@ char *process_args(int argc, char **argv)
case 'x':
fprintf(stderr, "enabling Zfinx support.\n");
rv_enable_zfinx = true;
zzzfinx_en = 1;
break;
case '?':
print_usage(argv[0], 1);
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104 changes: 68 additions & 36 deletions model/riscv_fdext_regs.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -187,40 +187,72 @@ overload to_str = {freg_name_abi}

/* mappings for assembly */

val freg_name : bits(5) <-> string
val freg_name : bits(6) <-> string
mapping freg_name = {
0b00000 <-> "ft0",
0b00001 <-> "ft1",
0b00010 <-> "ft2",
0b00011 <-> "ft3",
0b00100 <-> "ft4",
0b00101 <-> "ft5",
0b00110 <-> "ft6",
0b00111 <-> "ft7",
0b01000 <-> "fs0",
0b01001 <-> "fs1",
0b01010 <-> "fa0",
0b01011 <-> "fa1",
0b01100 <-> "fa2",
0b01101 <-> "fa3",
0b01110 <-> "fa4",
0b01111 <-> "fa5",
0b10000 <-> "fa6",
0b10001 <-> "fa7",
0b10010 <-> "fs2",
0b10011 <-> "fs3",
0b10100 <-> "fs4",
0b10101 <-> "fs5",
0b10110 <-> "fs6",
0b10111 <-> "fs7",
0b11000 <-> "fs8",
0b11001 <-> "fs9",
0b11010 <-> "fs10",
0b11011 <-> "fs11",
0b11100 <-> "ft8",
0b11101 <-> "ft9",
0b11110 <-> "ft10",
0b11111 <-> "ft11"
0b000000 <-> "ft0",
0b000001 <-> "ft1",
0b000010 <-> "ft2",
0b000011 <-> "ft3",
0b000100 <-> "ft4",
0b000101 <-> "ft5",
0b000110 <-> "ft6",
0b000111 <-> "ft7",
0b001000 <-> "fs0",
0b001001 <-> "fs1",
0b001010 <-> "fa0",
0b001011 <-> "fa1",
0b001100 <-> "fa2",
0b001101 <-> "fa3",
0b001110 <-> "fa4",
0b001111 <-> "fa5",
0b010000 <-> "fa6",
0b010001 <-> "fa7",
0b010010 <-> "fs2",
0b010011 <-> "fs3",
0b010100 <-> "fs4",
0b010101 <-> "fs5",
0b010110 <-> "fs6",
0b010111 <-> "fs7",
0b011000 <-> "fs8",
0b011001 <-> "fs9",
0b011010 <-> "fs10",
0b011011 <-> "fs11",
0b011100 <-> "ft8",
0b011101 <-> "ft9",
0b011110 <-> "ft10",
0b011111 <-> "ft11",
0b100000 <-> "zero",
0b100001 <-> "ra",
0b100010 <-> "sp",
0b100011 <-> "gp",
0b100100 <-> "tp",
0b100101 <-> "t0",
0b100110 <-> "t1",
0b100111 <-> "t2",
0b101000 <-> "fp",
0b101001 <-> "s1",
0b101010 <-> "a0",
0b101011 <-> "a1",
0b101100 <-> "a2",
0b101101 <-> "a3",
0b101110 <-> "a4",
0b101111 <-> "a5",
0b110000 <-> "a6",
0b110001 <-> "a7",
0b110010 <-> "s2",
0b110011 <-> "s3",
0b110100 <-> "s4",
0b110101 <-> "s5",
0b110110 <-> "s6",
0b110111 <-> "s7",
0b111000 <-> "s8",
0b111001 <-> "s9",
0b111010 <-> "s10",
0b111011 <-> "s11",
0b111100 <-> "t3",
0b111101 <-> "t4",
0b111110 <-> "t5",
0b111111 <-> "t6"
}

val init_fdext_regs : unit -> unit effect {wreg}
Expand Down Expand Up @@ -278,13 +310,13 @@ function ext_write_fcsr (frm, fflags) = {
fcsr->FRM() = frm; /* Note: frm can be an illegal value, 101, 110, 111 */
fcsr->FFLAGS() = fflags;
update_softfloat_fflags(fflags);
dirty_fd_context();
if (sys_enable_zfinx()==false) then dirty_fd_context();
}

/* called for softfloat paths (softfloat flags are consistent) */
val write_fflags : (bits(5)) -> unit effect {rreg, wreg}
function write_fflags(fflags) = {
if fcsr.FFLAGS() != fflags
if (fcsr.FFLAGS() != fflags & sys_enable_zfinx() == false)
then dirty_fd_context();
fcsr->FFLAGS() = fflags;
}
Expand All @@ -297,6 +329,6 @@ function accrue_fflags(flags) = {
then {
fcsr->FFLAGS() = f;
update_softfloat_fflags(f);
dirty_fd_context();
if (sys_enable_zfinx()==false) then dirty_fd_context();
}
}
92 changes: 46 additions & 46 deletions model/riscv_insts_dext.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ function fmake_D (sign, exp, mant) = sign @ exp @ mant
function canonical_NaN_D() -> bits(64) = 0x_7ff8_0000_0000_0000

/*Retrive the correct value for RV32D*/
val Xd : bits(5)-> bits(64)
val Xd : bits(5)-> bits(64) effect {escape, rreg}
function Xd index =
if (sizeof(xlen) == 64)
then X(index)
Expand Down Expand Up @@ -303,10 +303,10 @@ mapping f_madd_type_mnemonic_D : f_madd_op_D <-> string = {

mapping clause assembly = F_MADD_TYPE_D(rs3, rs2, rs1, rm, rd, op)
<-> f_madd_type_mnemonic_D(op)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ sep() ^ freg_name(rs3)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)
^ sep() ^ freg_name(zfinx_en@rs3)
^ sep() ^ frm_mnemonic(rm)

/* ****************************************************************** */
Expand Down Expand Up @@ -380,9 +380,9 @@ mapping f_bin_rm_type_mnemonic_D : f_bin_rm_op_D <-> string = {

mapping clause assembly = F_BIN_RM_TYPE_D(rs2, rs1, rm, rd, op)
<-> f_bin_rm_type_mnemonic_D(op)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)
^ sep() ^ frm_mnemonic(rm)

/* ****************************************************************** */
Expand Down Expand Up @@ -703,68 +703,68 @@ mapping f_un_rm_type_mnemonic_D : f_un_rm_op_D <-> string = {

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FSQRT_D)
<-> f_un_rm_type_mnemonic_D(FSQRT_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_W_D)
<-> f_un_rm_type_mnemonic_D(FCVT_W_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_WU_D)
<-> f_un_rm_type_mnemonic_D(FCVT_WU_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_W)
<-> f_un_rm_type_mnemonic_D(FCVT_D_W)
^ spc() ^ freg_name(rd)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ reg_name(rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_WU)
<-> f_un_rm_type_mnemonic_D(FCVT_D_WU)
^ spc() ^ freg_name(rd)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ reg_name(rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)
<-> f_un_rm_type_mnemonic_D(FCVT_L_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)
<-> f_un_rm_type_mnemonic_D(FCVT_LU_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)
<-> f_un_rm_type_mnemonic_D(FCVT_D_L)
^ spc() ^ freg_name(rd)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ reg_name(rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)
<-> f_un_rm_type_mnemonic_D(FCVT_D_LU)
^ spc() ^ freg_name(rd)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ reg_name(rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_S_D)
<-> f_un_rm_type_mnemonic_D(FCVT_S_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

mapping clause assembly = F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S)
<-> f_un_rm_type_mnemonic_D(FCVT_D_S)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ frm_mnemonic(rm)

/* ****************************************************************** */
Expand Down Expand Up @@ -1048,51 +1048,51 @@ mapping f_bin_type_mnemonic_D : f_bin_op_D <-> string = {

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJ_D)
<-> f_bin_type_mnemonic_D(FSGNJ_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJN_D)
<-> f_bin_type_mnemonic_D(FSGNJN_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FSGNJX_D)
<-> f_bin_type_mnemonic_D(FSGNJX_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FMIN_D)
<-> f_bin_type_mnemonic_D(FMIN_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FMAX_D)
<-> f_bin_type_mnemonic_D(FMAX_D)
^ spc() ^ freg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FEQ_D)
<-> f_bin_type_mnemonic_D(FEQ_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FLT_D)
<-> f_bin_type_mnemonic_D(FLT_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

mapping clause assembly = F_BIN_TYPE_D(rs2, rs1, rd, FLE_D)
<-> f_bin_type_mnemonic_D(FLE_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(rs2)
^ sep() ^ freg_name(zfinx_en@rs1)
^ sep() ^ freg_name(zfinx_en@rs2)

/* ****************************************************************** */
/* Unary, no rounding mode */
Expand Down Expand Up @@ -1183,16 +1183,16 @@ mapping f_un_type_mnemonic_D : f_un_op_D <-> string = {
mapping clause assembly = F_UN_TYPE_D(rs1, rd, FMV_X_D)
<-> f_un_type_mnemonic_D(FMV_X_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)

mapping clause assembly = F_UN_TYPE_D(rs1, rd, FMV_D_X)
<-> f_un_type_mnemonic_D(FMV_D_X)
^ spc() ^ freg_name(rd)
^ spc() ^ freg_name(zfinx_en@rd)
^ sep() ^ reg_name(rs1)

mapping clause assembly = F_UN_TYPE_D(rs1, rd, FCLASS_D)
<-> f_un_type_mnemonic_D(FCLASS_D)
^ spc() ^ reg_name(rd)
^ sep() ^ freg_name(rs1)
^ sep() ^ freg_name(zfinx_en@rs1)

/* ****************************************************************** */

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