revert to CM.JALT/CM.JT for RC5

riscvarchive · Sep 8, 2022 · 3736732 · 3736732
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diff --git a/Zc-specification/Zc.adoc b/Zc-specification/Zc.adoc
@@ -1,13 +1,14 @@
 :sectnums:
 [#Zc]
-== Zc* v1.0.0-RC4.1
+== Zc* v1.0.0-RC5
 
 === Change history since v0.70.1 (tagged release)
 
 .Change history
 [width="100%",options=header]
 |====================================================================================
 |Version  | change
+|v1.0.0-RC5| Revert to cm.jt and cm.jalt encodings, to avoid toolchain and trace problems
 |v1.0.0-RC4.1| Resolve typographical issues with the document only, no actual changes
 |v1.0.0-RC4| Release candidate
 |         | Remove Zcmb as benefit is low. Remove cm.jalt, read LSB of jump table entry to determine whether to link
@@ -75,6 +76,7 @@ Zcm* all reuse the encodings for _c.fld_, _c.fsd_, _c.fldsp_, _c.fsdsp_.
 |cm.mva01s.e    |        |        |        |        |        |yes     | 
 |cm.mvsa01.e    |        |        |        |        |        |yes     | 
 8+|*Table jump*              
+|cm.jt          |        |        |        |        |        |        |yes     
 |cm.jalt        |        |        |        |        |        |        |yes     
 |====================================================================================
 
@@ -280,6 +282,11 @@ Zcmt requires the <<Zca>> extension.
 |Mnemonic
 |Instruction
 
+|yes     
+|yes     
+|cm.jt _index_
+|<<#insns-cm_jt>> 
+
 |yes     
 |yes     
 |cm.jalt _index_
@@ -311,5 +318,6 @@ include::cm_mva01s.adoc[]
 
 include::tablejump.adoc[]
 include::jvt_csr.adoc[]
+include::cm_jt.adoc[]
 include::cm_jalt.adoc[]
 
diff --git a/Zc-specification/Zcb_footer.adoc b/Zc-specification/Zcb_footer.adoc
@@ -7,6 +7,6 @@ Included in::
 |Lifecycle state
 
 |Zcb (<<Zcb>>)
-|v1.0.0-RC4.1
+|v1.0.0-RC5
 |Stable
 |===
diff --git a/Zc-specification/Zcf_footer.adoc b/Zc-specification/Zcf_footer.adoc
@@ -7,6 +7,6 @@ Included in::
 |Lifecycle state
 
 |Zcf (<<Zcf>>)
-|v1.0.0-RC4.1
+|v1.0.0-RC5
 |Frozen
 |===
diff --git a/Zc-specification/Zcmp_footer.adoc b/Zc-specification/Zcmp_footer.adoc
@@ -7,6 +7,6 @@ Included in::
 |Lifecycle state
 
 |Zcmp (<<Zcmp>>)
-|v1.0.0-RC4.1
+|v1.0.0-RC5
 |Stable
 |===
diff --git a/Zc-specification/Zcmpe_footer.adoc b/Zc-specification/Zcmpe_footer.adoc
@@ -7,6 +7,6 @@ Included in::
 |Lifecycle state
 
 |Zcmpe (<<Zcmpe>>)
-|v1.0.0-RC4.1
+|v1.0.0-RC5
 |Stable
 |===
diff --git a/Zc-specification/Zcmt_footer.adoc b/Zc-specification/Zcmt_footer.adoc
@@ -7,6 +7,6 @@ Included in::
 |Lifecycle state
 
 |Zcmt (<<Zcmt>>)
-|v1.0.0-RC4.1
+|v1.0.0-RC5
 |Frozen
 |===
diff --git a/Zc-specification/cm_jalt.adoc b/Zc-specification/cm_jalt.adoc
@@ -1,5 +1,5 @@
 <<<
-[#insns-cm_jalt,reftext="Jump via table with optional link"]
+[#insns-cm_jalt,reftext="Jump and link via table"]
 === cm.jalt
 
 Synopsis::
@@ -19,6 +19,10 @@ Encoding (RV32, RV64)::
 ],config:{bits:16}}
 ....
 
+[NOTE]
+
+  For this encoding to decode as _cm.jalt_, _index>=64_, otherwise it decodes as _cm.jt_, see <<insns-cm_jt>>.
+
 Assembly Syntax::
 
 [source,sail]
@@ -28,9 +32,7 @@ cm.jalt index
 
 Description::
 
-_cm.jalt_ reads an entry from the jump vector table in memory and jumps to the address that was read. If the LSB of the table entry is 0 then link to ra, otherwise don't link.
-
-_cm.jalt_ is reserved if executing from a mode with higher privilege than user mode where the current XLEN does not match UXLEN.
+_cm.jalt_ reads an entry from the jump vector table in memory and jumps to the address that was read, linking to _ra_.
 
 For further information see <<insns-tablejump>>.
 
@@ -49,11 +51,6 @@ Operation::
 --
 //This is not SAIL, it's pseudo-code. The SAIL hasn't been written yet.
 
-if (mode==M  && MXLEN !=UXLEN) reserved();
-if (mode==S  && SXLEN !=UXLEN) reserved();
-if (mode==HS && HSXLEN!=UXLEN) reserved();
-if (mode==VS && VSXLEN!=UXLEN) reserved();
-
 # target_address is temporary internal state, it doesn't represent a real register
 # InstMemory is byte indexed
 
@@ -65,11 +62,7 @@ switch(XLEN) {
 //fetch from the jump table
 target_address[XLEN-1:0] = InstMemory[table_address][XLEN-1:0];
 
-//jump to the target address, check the LSB to see whether to link
-if (target_address[0]==1'b0)
-  jalr target_address[XLEN-1:0]&~0x1;
-else
-  jr   target_address[XLEN-1:0]&~0x1;
+jal ra, target_address[XLEN-1:0]&~0x1;
 
 --
 

diff --git a/Zc-specification/cm_jt.adoc b/Zc-specification/cm_jt.adoc
@@ -1,9 +1,9 @@
 <<<
-[#insns-cm_jt,reftext="Jump via table with optional link"]
+[#insns-cm_jt,reftext="Jump via table"]
 === cm.jt
 
 Synopsis::
-jump via table with optional link
+jump via table
 
 Mnemonic::
 cm.jt _index_
@@ -19,6 +19,10 @@ Encoding (RV32, RV64)::
 ],config:{bits:16}}
 ....
 
+[NOTE]
+
+  For this encoding to decode as _cm.jt_, _index<64_, otherwise it decodes as _cm.jalt_, see <<insns-cm_jalt>>.
+
 Assembly Syntax::
 
 [source,sail]
@@ -28,7 +32,7 @@ cm.jt index
 
 Description::
 
-_cm.jt_ reads an entry from the jump vector table in memory and jumps to the address that was read. If the LSB of the table entry is 1 then link to ra, otherwise don't link.
+_cm.jt_ reads an entry from the jump vector table in memory and jumps to the address that was read.
 
 For further information see <<insns-tablejump>>.
 
@@ -58,11 +62,7 @@ switch(XLEN) {
 //fetch from the jump table
 target_address[XLEN-1:0] = InstMemory[table_address][XLEN-1:0];
 
-//jump to the target address, check the LSB to see whether to link
-if (target_address[0]==1'b1)
-  jalr target_address[XLEN-1:0]&~0x1;
-else
-  jr   target_address[XLEN-1:0]&~0x1;
+j target_address[XLEN-1:0]&~0x1;
 
 --
 

diff --git a/Zc-specification/jvt_csr.adoc b/Zc-specification/jvt_csr.adoc
@@ -31,7 +31,7 @@ Format (RV64)::
 
 Description::
 
-The _JVT_ register is an UXLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
+The _JVT_ register is an XLEN-bit *WARL* read/write register that holds the jump table configuration, consisting of the jump table base address (BASE) and the jump table mode (MODE).
 
 If <<Zcmt>> is implemented then _JVT_ must also be implemented, but can contain a read-only value. If _JVT_ is writable, the set of values the register may hold can vary by implementation. The value in the BASE field must always be aligned on a 64-byte boundary.
 

diff --git a/Zc-specification/tablejump.adoc b/Zc-specification/tablejump.adoc
@@ -3,29 +3,30 @@
 [#insns-tablejump,reftext="Table Jump Overview"]
 == Table Jump Overview
 
-<<#insns-cm_jalt>> is referred to as table jump.
+_cm.jt_ (<<#insns-cm_jt>>) and _cm.jalt_ (<<#insns-cm_jalt>>) are referred to as table jump.
 
-Table jump uses a 256-entry UXLEN wide table in instruction memory to contain function addresses, 
-and a flag in bit zero of each entry indicating whether jumping to the function address should link or not.
+Table jump uses a 256-entry XLEN wide table in instruction memory to contain function addresses.
 The table must be a minimum of 64-byte aligned.
 
-_cm.jalt_ encodings index the table, giving access to functions within the full UXLEN wide address space.
+Table entries follow the current data endianness. This is different from normal instruction fetch which is always little-endian.
 
-This is used as a form of dictionary compression used to reduce the code size of _jal_ / _auipc+jalr_ / _jr_ / _auipc+jr_ instructions.
+_cm.jt_ and _cm.jalt_ encodings index the table, giving access to functions within the full XLEN wide address space.
 
-Table jump allows the linker to replace the following instruction sequences with a _cm.jalt_ encoding, and an entry in the table:
+This is used as a form of dictionary compression to reduce the code size of _jal_ / _auipc+jalr_ / _jr_ / _auipc+jr_ instructions.
+
+Table jump allows the linker to replace the following instruction sequences with a _cm.jt_ or _cm.jalt_ encoding, and an entry in the table:
 
 * 32-bit _j_ calls 
 * 32-bit _jal_ ra calls 
 * 64-bit _auipc+jr_ calls to fixed locations 
 * 64-bit _auipc+jalr ra_ calls to fixed locations 
 ** The _auipc+jr/jalr_ sequence is used because the offset from the PC is out of the ±1MB range.
 
-=== JVT
+If a return address stack is implemented, then as _cm.jalt_ is equivalent to _jal ra_, it pushes to the stack.
 
-The base of the table is in the JVT CSR (see <<csrs-jvt>>), each table entry is UXLEN bits.
+=== JVT
 
-Bit zero of every table entry indicates whether to update the link register.
+The base of the table is in the JVT CSR (see <<csrs-jvt>>), each table entry is XLEN bits.
 
 If the same function is called with and without linking then it must have two entries in the table. 
 This is typically caused by the same function being called with and without tail calling.
@@ -34,7 +35,7 @@ This is typically caused by the same function being called with and without tail
 === Table Jump Fault handling
 
 For a table jump instruction, the table entry that the instruction selects is considered an extension of the instruction itself.
-Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (_cm.jalt_) 
+Hence, the execution of a table jump instruction involves two instruction fetches, the first to read the instruction (_cm.jt_/_cm.jalt_) 
 and the second to read from the jump vector table (JVT). Both instruction fetches are _implicit_ reads, and both require
 execute permission; read permission is irrelevant. It is recommended that the second fetch be ignored for hardware triggers and breakpoints.