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210 changes: 79 additions & 131 deletions Zc-specification/Zc.adoc
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@@ -1,96 +1,108 @@
:sectnums:
[#Zc]
== Zc* v0.70.5
== Zc* v1.0.0-RC4

=== Change history since v0.70.1 (tagged release)

.Change history
[width="100%",options=header]
|====================================================================================
|Version | change
|v0.70.5 | Resolve https://github.com/riscv/riscv-code-size-reduction/issues/163 - jvt.base is WARL and fewer bits than the max can be implemented
|v0.70.4 | Clarified https://github.com/riscv/riscv-code-size-reduction/issues/159 - Need Zbb and Zba for RV64 and M/ZMmul to get _all_ of Zcb
| | Resolved https://github.com/riscv/riscv-code-size-reduction/issues/161
| | Resolved https://github.com/riscv/riscv-code-size-reduction/issues/160 - Allocated Smstateen bit 2 and added the relevant text
|v0.70.3 | Added rule that Zcf and Zcmt imply Zca (this text was missing, this is not a spec change: https://github.com/riscv/riscv-code-size-reduction/pull/151)
| | Added that Zcf is illegal for RV64, as it contains no instructions (clarification: https://github.com/riscv/riscv-code-size-reduction/issues/149)
| | Added push/pop examples in the push/pop section
|v0.70.2 | Stylistic changes only, removing redundant text.
| | Corrected field names on JVT CSR diagram, and fixed synopsis for cm.mvsa01
|Version | change
|v1.0.0-RC4| Release candidate
| | Remove Zcmb as benefit is low. Remove cm.jalt, read LSB of jump table entry to determine whether to link
|v0.70.5 | Resolve https://github.com/riscv/riscv-code-size-reduction/issues/163 - jvt.base is WARL and fewer bits than the max can be implemented
|v0.70.4 | Clarified https://github.com/riscv/riscv-code-size-reduction/issues/159 - Need Zbb and Zba for RV64 and M/ZMmul to get _all_ of Zcb
| | Resolved https://github.com/riscv/riscv-code-size-reduction/issues/161
| | Resolved https://github.com/riscv/riscv-code-size-reduction/issues/160 - Allocated Smstateen bit 2 and added the relevant text
|v0.70.3 | Added rule that Zcf and Zcmt imply Zca (this text was missing, this is not a spec change: https://github.com/riscv/riscv-code-size-reduction/pull/151)
| | Added that Zcf is illegal for RV64, as it contains no instructions (clarification: https://github.com/riscv/riscv-code-size-reduction/issues/149)
| | Added push/pop examples in the push/pop section
|v0.70.2 | Stylistic changes only, removing redundant text.
| | Corrected field names on JVT CSR diagram, and fixed synopsis for cm.mvsa01
|====================================================================================

=== Zc* Overview

This document is in the Stable state. Assume anything could still change, but limited change should be expected. For more information see:
https://riscv.org/spec-state

Zc* is a group of extensions which define subsets of the existing C extension (Zca, Zcf) and new extensions which only contain 16-bit encodings.
Zc* is a group of extensions which define subsets of the existing C extension (Zca, Zcd, Zcf) and new extensions which only contain 16-bit encodings.

Zcm* all reuse the encodings for _c.fld_, _c.fsd_, _c.fldsp_, _c.fsdsp_.

.Zc* extension overview
[width="100%",options=header]
|====================================================================================
|Instruction |Zca|Zcf|Zcb|Zcmb|Zcmp|Zcmpe|Zcmt
8+|*Define a subset of C with the floating point load/stores removed*
|C excl. c.f* |✓| | | | | |
8+|*The single precision floating point load/stores become a separate extension*
|c.flw | |✓| | | | |
|c.flwsp | |✓| | | | |
|c.fsw | |✓| | | | |
|c.fswsp | |✓| | | | |
|Instruction |Zca |Zcf |Zcd |Zcb |Zcmp |Zcmpe |Zcmt
8+|*The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores*
|C excl. c.f* |✓| | | | | |
8+|*The Zcf extension is added as a way to refer to compressed single-precision floating-point load/stores*
|c.flw | |✓| | | | |
|c.flwsp | |✓| | | | |
|c.fsw | |✓| | | | |
|c.fswsp | |✓| | | | |
8+|*The Zcd extension is added as a way to refer to compressed double-precision floating-point load/stores*
|c.fld | | |✓| | | |
|c.fldsp | | |✓| | | |
|c.fsd | | |✓| | | |
|c.fsdsp | | |✓| | | |
8+|*Simple operations for use on all architectures*
|c.lbu | | |✓| | | |
|c.lh | | |✓| | | |
|c.lhu | | |✓| | | |
|c.sb | | |✓| | | |
|c.sh | | |✓| | | |
|c.zext.b | | |✓| | | |
|c.sext.b | | |✓| | | |
|c.zext.h | | |✓| | | |
|c.sext.h | | |✓| | | |
|c.zext.w | | |✓| | | |
|c.mul | | |✓| | | |
|c.not | | |✓| | | |
8+|*Load/store byte/half which overlap with _c.fld_, _c.fldsp_, _c.fsd_*
|cm.lb | | | |✓ | | |
|cm.lbu | | | |✓ | | |
|cm.lh | | | |✓ | | |
|cm.lhu | | | |✓ | | |
|cm.sb | | | |✓ | | |
|cm.sh | | | |✓ | | |
|c.lbu | | | |✓| | |
|c.lh | | | |✓| | |
|c.lhu | | | |✓| | |
|c.sb | | | |✓| | |
|c.sh | | | |✓| | |
|c.zext.b | | | |✓| | |
|c.sext.b | | | |✓| | |
|c.zext.h | | | |✓| | |
|c.sext.h | | | |✓| | |
|c.zext.w | | | |✓| | |
|c.mul | | | |✓| | |
|c.not | | | |✓| | |
8+|*PUSH/POP and double move which overlap with _c.fsdsp_*
|cm.push | | | | |✓ | ✓ |
|cm.pop | | | | |✓ | ✓ |
|cm.popret | | | | |✓ | ✓ |
|cm.popretz | | | | |✓ | ✓ |
|cm.mva01s | | | | |✓ | |
|cm.mvsa01 | | | | |✓ | |
|cm.push | | | | |✓|✓|
|cm.pop | | | | |✓|✓|
|cm.popret | | | | |✓|✓|
|cm.popretz | | | | |✓|✓|
|cm.mva01s | | | | |✓| |
|cm.mvsa01 | | | | |✓| |
8+|*Reserved for EABI versions of PUSH/POP and double move which overlap with _c.fsdsp_*
|cm.push.e | | | | | | ✓ |
|cm.pop.e | | | | | | ✓ |
|cm.popret.e | | | | | | ✓ |
|cm.popretz.e | | | | | | ✓ |
|cm.mva01s.e | | | | | | ✓ |
|cm.mvsa01.e | | | | | | ✓ |
8+|*Table jump*
|cm.jt | | | | | | |✓
|cm.jalt | | | | | | |✓
|cm.push.e | | | | | |✓|
|cm.pop.e | | | | | |✓|
|cm.popret.e | | | | | |✓|
|cm.popretz.e | | | | | |✓|
|cm.mva01s.e | | | | | |✓|
|cm.mvsa01.e | | | | | |✓|
8+|*Table jump*
|cm.jalt | | | | | |✓
|====================================================================================

[#Zca]
=== Zca

Zca is all of the existing C extension, _excluding_ all 16-bit floating point loads and stores: _c.flw_, _c.flwsp_, _c.fsw_, _c.fswsp_, _c.fld_, _c.fldsp_, _c.fsd_, _c.fsdsp_.
The Zca extension is added as way to refer to instructions in the C extension that do not include the floating-point loads and stores.

Therefore it _excluded_ all 16-bit floating point loads and stores: _c.flw_, _c.flwsp_, _c.fsw_, _c.fswsp_, _c.fld_, _c.fldsp_, _c.fsd_, _c.fsdsp_.

NOTE: the the C extension only includes F/D instructions when D and F are also specified

[#Zcf]
=== Zcf (RV32 only)

Zcf is the existing set of single precision floating point loads and stores: _c.flw_, _c.flwsp_, _c.fsw_, _c.fswsp_.
Zcf is the existing set of compressed single precision floating point loads and stores: _c.flw_, _c.flwsp_, _c.fsw_, _c.fswsp_.

Zcf is only relevant to RV32, it cannot be specified for RV64.

Zcf requires the <<Zca>> extension.

[#Zcd]
=== Zcd

Zcd is the existing set of compressed double precision floating point loads and stores: _c.fld_, _c.fldsp_, _c.fsd_, _c.fsdsp_.

Zcd requires the <<Zca>> extension.


<<<

[#Zcb]
Expand Down Expand Up @@ -179,64 +191,13 @@ The _c.mul_ encoding uses the CR register format along with other instructions s

<<<

[#Zcmb]
=== Zcmb

This extension reuses some encodings from _c.fld_, _c.fldsp_, and _c.fsd_. Therefore it is _incompatible_ with the full C-extension.
It is compatible with F, D with Zdinx.

Zcmb requires the <<Zcb>> extension, which in turn requires the <<Zca>> extension.

The instructions are all 16-bit versions of existing 32-bit load/store instructions.

[%header,cols="^1,^1,4,8"]
|===
|RV32
|RV64
|Mnemonic
|Instruction

|&#10003;
|&#10003;
|cm.lbu _rd'_, uimm(_rs1'_)
|<<#insns-cm_lbu>>

|&#10003;
|&#10003;
|cm.lhu _rd'_, uimm(_rs1'_)
|<<#insns-cm_lhu>>

|&#10003;
|&#10003;
|cm.lb _rd'_, uimm(_rs1'_)
|<<#insns-cm_lb>>

|&#10003;
|&#10003;
|cm.lh _rd'_, uimm(_rs1'_)
|<<#insns-cm_lh>>

|&#10003;
|&#10003;
|cm.sb _rs2'_, uimm(_rs1'_)
|<<#insns-cm_sb>>

|&#10003;
|&#10003;
|cm.sh _rs2'_, uimm(_rs1'_)
|<<#insns-cm_sh>>

|===

<<<

[#Zcmp]
=== Zcmp

Zcmp is the set of sequenced instuctions for code-size reduction.
The Zcmp extension is a set of instuctions which may be executed as a series of existing 32-bit RISC-V instructions.

This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with the full C-extension.
It is compatible with F, D with Zdinx.
This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <<Zcd>>,
which is included when C and D extensions are both present.

Zcmp requires the <<Zca>> extension.

Expand Down Expand Up @@ -292,12 +253,12 @@ The PUSH/POP assembly syntax uses several variables, the meaning of which are:
[#Zcmpe]
=== Zcmpe

This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with the full C-extension.
It is compatible with F, D with Zdinx.
The Zcmpe extension offers EABI support for register mappings from <<Zcmp>> where the _x_ register mapping is different to the UABI.

Zcmpe requires the <<Zca>> extension.
This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <<Zcd>>,
which is included when C and D extensions are both present.

Zcmpe offers EABI support for register mappings from <<Zcmp>> where the _x_ register mapping is different to the UABI.
Zcmpe requires the <<Zca>> extension.

[NOTE]

Expand All @@ -306,12 +267,12 @@ Zcmpe offers EABI support for register mappings from <<Zcmp>> where the _x_ regi
[#Zcmt]
=== Zcmt

This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with the full C-extension.
It is compatible with F, D with Zdinx.

Zcmt is the set of table jump instuctions for code-size reduction, and also adds the JVT CSR. The JVT CSR requires a
Zcmt adds a table jump instuction and also adds the JVT CSR. The JVT CSR requires a
state enable if Smstateen is implemented. See <<csrs-jvt>> for details.

This extension reuses some encodings from _c.fsdsp_. Therefore it is _incompatible_ with <<Zcd>>,
which is included when C and D extensions are both present.

Zcmt requires the <<Zca>> extension.

[%header,cols="^1,^1,4,8"]
Expand All @@ -321,11 +282,6 @@ Zcmt requires the <<Zca>> extension.
|Mnemonic
|Instruction

|&#10003;
|&#10003;
|cm.jt _index_
|<<#insns-cm_jt>>

|&#10003;
|&#10003;
|cm.jalt _index_
Expand All @@ -347,13 +303,6 @@ include::c_zext_w.adoc[]
include::c_not.adoc[]
include::c_mul.adoc[]

include::cm_lbu.adoc[]
include::cm_lhu.adoc[]
include::cm_lb.adoc[]
include::cm_lh.adoc[]
include::cm_sb.adoc[]
include::cm_sh.adoc[]

include::pushpop.adoc[]
include::cm_push.adoc[]
include::cm_pop.adoc[]
Expand All @@ -364,6 +313,5 @@ include::cm_mva01s.adoc[]

include::tablejump.adoc[]
include::jvt_csr.adoc[]
include::cm_jt.adoc[]
include::cm_jalt.adoc[]

2 changes: 1 addition & 1 deletion Zc-specification/Zcb_footer.adoc
View file
Expand Up @@ -7,6 +7,6 @@ Included in::
|Lifecycle state

|Zcb (<<Zcb>>)
|v0.70.5
|v1.0.0-RC3
|Stable
|===
4 changes: 2 additions & 2 deletions Zc-specification/Zcf_footer.adoc
View file
Expand Up @@ -7,6 +7,6 @@ Included in::
|Lifecycle state

|Zcf (<<Zcf>>)
|v0.70.5
|Stable
|v1.0.0-RC4
|Frozen
|===
2 changes: 1 addition & 1 deletion Zc-specification/Zcmp_footer.adoc
View file
Expand Up @@ -7,6 +7,6 @@ Included in::
|Lifecycle state

|Zcmp (<<Zcmp>>)
|v0.70.5
|v1.0.0-RC3
|Stable
|===
2 changes: 1 addition & 1 deletion Zc-specification/Zcmpe_footer.adoc
View file
Expand Up @@ -7,6 +7,6 @@ Included in::
|Lifecycle state

|Zcmpe (<<Zcmpe>>)
|v0.70.5
|v1.0.0-RC4
|Stable
|===
4 changes: 2 additions & 2 deletions Zc-specification/Zcmt_footer.adoc
View file
Expand Up @@ -7,6 +7,6 @@ Included in::
|Lifecycle state

|Zcmt (<<Zcmt>>)
|v0.70.5
|Stable
|v1.0.0-RC4
|Frozen
|===
8 changes: 1 addition & 7 deletions Zc-specification/c_lbu.adoc
View file
@@ -1,5 +1,5 @@
<<<
[#insns-c_lbu,reftext="c.lbu: Load unsigned byte, 16-bit encoding"]
[#insns-c_lbu,reftext="Load unsigned byte, 16-bit encoding"]
=== c.lbu

Synopsis::
Expand Down Expand Up @@ -29,12 +29,6 @@ This instruction loads a byte from the memory address formed by adding _rs1'_ to
[NOTE]
_rd'_ and _rs1'_ are from the standard 8-register set x8-x15.

[NOTE]
For an longer immediate with a 16-bit encoding see <<insns-cm_lbu>>.

[NOTE]
To load _signed_ bytes with a 16-bit encoding see <<insns-cm_lb>>.

Prerequisites::
None

Expand Down
5 changes: 1 addition & 4 deletions Zc-specification/c_lh.adoc
View file
@@ -1,5 +1,5 @@
<<<
[#insns-c_lh,reftext="c.lh: Load signed halfword, 16-bit encoding"]
[#insns-c_lh,reftext="Load signed halfword, 16-bit encoding"]
=== c.lh

Synopsis::
Expand Down Expand Up @@ -30,9 +30,6 @@ This instruction loads a halfword from the memory address formed by adding _rs1'
[NOTE]
_rd'_ and _rs1'_ are from the standard 8-register set x8-x15.

[NOTE]
For an longer immediate with a 16-bit encoding see <<insns-cm_lh>>.

Prerequisites::
None

Expand Down
5 changes: 1 addition & 4 deletions Zc-specification/c_lhu.adoc
View file
@@ -1,5 +1,5 @@
<<<
[#insns-c_lhu,reftext="c.lhu: Load unsigned halfword, 16-bit encoding"]
[#insns-c_lhu,reftext="Load unsigned halfword, 16-bit encoding"]
=== c.lhu

Synopsis::
Expand Down Expand Up @@ -30,9 +30,6 @@ This instruction loads a halfword from the memory address formed by adding _rs1'
[NOTE]
_rd'_ and _rs1'_ are from the standard 8-register set x8-x15.

[NOTE]
For an longer immediate with a 16-bit encoding see <<insns-cm_lhu>>.

Prerequisites::
None

Expand Down

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