MIPS

MIPS(Microprocessor without interlocked pipeline stages) processor implementation in VHDL.

Description

Single Cycle Implementation

In the MIPS single cycle implementation, all instructions complete in exactly one cycle(and just one instruction complete in one cycle).

Pipeline Implementation

With MIPS pipeline, the processor is divided in isolated pipeline stages. Each one of that stages can perform simultaneously, and doing that, multiple instructions run at the same time, in different stages.

Authors

• Rodrigo Masaru Ohashi - rmohashi
• Bruno Eidi Nishimoto - brunonishimoto
• Matheus Felix Dias Lima da Silva - matheusssf

References

• Fundamentals of Computer Systems - A Pipelined MIPS Processor