12654 nxge: smatch and NULL pointer errors

Reviewed by: Michael Speer <michael.speer@pluribusnetworks.com>
Reviewed by: Yuri Pankov <ypankov@tintri.com>
Reviewed by: Igor Kozhukhov <igor@dilos.org>
Reviewed by: Vitaliy Gusev <gusev.vitaliy@icloud.com>
Approved by: Dan McDonald <danmcd@joyent.com>

usr/src/uts/common/io/nxge/npi/npi_fflp.c

@@ -615,7 +615,7 @@ npi_fflp_fcram_entry_write(npi_handle_t handle, part_id_t partid,
 	switch (format) {
 	case FCRAM_ENTRY_OPTIM:
 		if (location % 8) {
-		/* need to be 8 byte alligned */
+		/* need to be 8 byte aligned */
 
 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
 				    " FCRAM_ENTRY_OOPTIM Write:"
@@ -631,31 +631,31 @@ npi_fflp_fcram_entry_write(npi_handle_t handle, part_id_t partid,
 
 	case FCRAM_ENTRY_EX_IP4:
 		if (location % 32) {
-/* need to be 32 byte alligned */
+			/* need to be 32 byte aligned */
 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
 			    " FCRAM_ENTRY_EX_IP4 Write:"
 			    " unaligned location %llx \n",
 			    location));
 			return (NPI_FFLP_FCRAM_LOC_INVALID);
-	}
+		}
 
-	num_subareas = 4;
-	autoinc = 1;
+		num_subareas = 4;
+		autoinc = 1;
 
-	break;
+		break;
 	case FCRAM_ENTRY_EX_IP6:
 		if (location % 64) {
-				/* need to be 64 byte alligned */
+			/* need to be 64 byte aligned */
 			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
-				    " FCRAM_ENTRY_EX_IP6 Write:"
-				    " unaligned location %llx \n",
-				    location));
-				return (NPI_FFLP_FCRAM_LOC_INVALID);
+			    " FCRAM_ENTRY_EX_IP6 Write:"
+			    " unaligned location %llx \n",
+			    location));
+			return (NPI_FFLP_FCRAM_LOC_INVALID);
 
 		}
 		num_subareas = 7;
 		autoinc = 1;
-			break;
+		break;
 	default:
 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
 			    " fcram_entry_write:"
@@ -713,23 +713,23 @@ npi_fflp_fcram_entry_read(npi_handle_t handle,  part_id_t partid,
 	switch (format) {
 		case FCRAM_ENTRY_OPTIM:
 			if (location % 8) {
-			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
-			    " FCRAM_ENTRY_OOPTIM Read:"
-			    " unaligned location %llx \n",
-			    location));
-			/* need to be 8 byte alligned */
+				NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
+				    " FCRAM_ENTRY_OOPTIM Read:"
+				    " unaligned location %llx \n",
+				    location));
+				/* need to be 8 byte aligned */
 				return (NPI_FFLP_FCRAM_LOC_INVALID);
 			}
 			num_subareas = 1;
 			autoinc = 0;
 			break;
 		case FCRAM_ENTRY_EX_IP4:
 			if (location % 32) {
-					/* need to be 32 byte alligned */
-			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
-			    " FCRAM_ENTRY_EX_IP4 READ:"
-			    " unaligned location %llx \n",
-			    location));
+				/* need to be 32 byte aligned */
+				NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
+				    " FCRAM_ENTRY_EX_IP4 READ:"
+				    " unaligned location %llx \n",
+				    location));
 				return (NPI_FFLP_FCRAM_LOC_INVALID);
 			}
 			num_subareas = 4;
@@ -738,24 +738,24 @@ npi_fflp_fcram_entry_read(npi_handle_t handle,  part_id_t partid,
 			break;
 		case FCRAM_ENTRY_EX_IP6:
 			if (location % 64) {
-					/* need to be 64 byte alligned */
-			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
-			    " FCRAM_ENTRY_EX_IP6 READ:"
-			    " unaligned location %llx \n",
-			    location));
+				/* need to be 64 byte aligned */
+				NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
+				    " FCRAM_ENTRY_EX_IP6 READ:"
+				    " unaligned location %llx \n",
+				    location));
 
 				return (NPI_FFLP_FCRAM_LOC_INVALID);
-	}
+			}
 			num_subareas = 7;
 			autoinc = 1;
 
 			break;
 		default:
-		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
-		    " fcram_entry_read:"
-		    " unknown format param location %llx\n",
-		    location));
-		return (NPI_FFLP_SW_PARAM_ERROR);
+			NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
+			    " fcram_entry_read:"
+			    " unknown format param location %llx\n",
+			    location));
+			return (NPI_FFLP_SW_PARAM_ERROR);
 	}
 
 	addr.value = 0;
@@ -867,7 +867,7 @@ npi_fflp_fcram_subarea_write(npi_handle_t handle, part_id_t partid,
 		    " fcram_subarea_write:"
 		    " unaligned location %llx \n",
 		    location));
-			/* need to be 8 byte alligned */
+			/* need to be 8 byte aligned */
 		return (NPI_FFLP_FCRAM_LOC_INVALID);
 	}
 
@@ -928,7 +928,7 @@ npi_fflp_fcram_subarea_read(npi_handle_t handle, part_id_t partid,
 				    " fcram_subarea_read:"
 				    " unaligned location %llx \n",
 				    location));
-			/* need to be 8 byte alligned */
+			/* need to be 8 byte aligned */
 		return (NPI_FFLP_FCRAM_LOC_INVALID);
 	}
 
@@ -958,19 +958,18 @@ npi_fflp_fcram_subarea_read(npi_handle_t handle, part_id_t partid,
 npi_status_t
 npi_fflp_cfg_fcram_partition(npi_handle_t handle, part_id_t partid,
 				    uint8_t base_mask, uint8_t base_reloc)
-
 {
-/*
- * assumes that the base mask and relocation are computed somewhere
- * and kept in the state data structure. Alternativiely, one can pass
- * a partition size and a starting address and this routine can compute
- * the mask and reloc vlaues.
- */
+	/*
+	 * assumes that the base mask and relocation are computed somewhere
+	 * and kept in the state data structure. Alternativiely, one can pass
+	 * a partition size and a starting address and this routine can compute
+	 * the mask and reloc vlaues.
+	 */
 
-    flow_prt_sel_t sel;
-    uint64_t offset;
+	flow_prt_sel_t sel;
+	uint64_t offset;
 
-    ASSERT(FCRAM_PARTITION_VALID(partid));
+	ASSERT(FCRAM_PARTITION_VALID(partid));
 	if (!FCRAM_PARTITION_VALID(partid)) {
 		NPI_ERROR_MSG((handle.function, NPI_ERR_CTL,
 				    " npi_fflp_cfg_fcram_partition:"
@@ -979,14 +978,13 @@ npi_fflp_cfg_fcram_partition(npi_handle_t handle, part_id_t partid,
 		return (NPI_FFLP_FCRAM_PART_INVALID);
 	}
 
-    offset = FFLP_PART_OFFSET(partid, FFLP_FLW_PRT_SEL_REG);
-    sel.value = 0;
-    sel.bits.ldw.mask = base_mask;
-    sel.bits.ldw.base = base_reloc;
-    sel.bits.ldw.ext = BIT_DISABLE; /* disable */
-    REG_PIO_WRITE64(handle, offset, sel.value);
-    return (NPI_SUCCESS);
-
+	offset = FFLP_PART_OFFSET(partid, FFLP_FLW_PRT_SEL_REG);
+	sel.value = 0;
+	sel.bits.ldw.mask = base_mask;
+	sel.bits.ldw.base = base_reloc;
+	sel.bits.ldw.ext = BIT_DISABLE; /* disable */
+	REG_PIO_WRITE64(handle, offset, sel.value);
+	return (NPI_SUCCESS);
 }
 
 /*
@@ -1572,7 +1570,7 @@ npi_fflp_cfg_enet_vlan_table_assoc(npi_handle_t handle, uint8_t mac_portn,
 			parity_bit = vlan_parity[cfg.bits.ldw.vlanrdctbln0] +
 			    vlan_parity[cfg.bits.ldw.vlanrdctbln1] +
 			    cfg.bits.ldw.vpr0 + cfg.bits.ldw.vpr1;
-				cfg.bits.ldw.parity0 = parity_bit & 0x1;
+			cfg.bits.ldw.parity0 = parity_bit & 0x1;
 
 			break;
 		case 2:

usr/src/uts/common/io/nxge/nxge_hio_guest.c

@@ -572,7 +572,7 @@ nxge_hio_vr_release(nxge_t *nxge)
 	MUTEX_ENTER(&nhd->lock);
 	for (vr_index = 0; vr_index < FUNC_VIR_MAX; vr_index++) {
 		if (nhd->vr[vr_index].nxge == (uintptr_t)nxge) {
-			nhd->vr[vr_index].nxge = NULL;
+			nhd->vr[vr_index].nxge = (uintptr_t)NULL;
 			break;
 		}
 	}

usr/src/uts/common/io/nxge/nxge_hw.c

@@ -203,6 +203,8 @@ nxge_intr(void *arg1, void *arg2)
 	int i, j, nldvs, nintrs = 1;
 	npi_status_t rs = NPI_SUCCESS;
 
+	VERIFY(ldvp != NULL);
+
 	/* DDI interface returns second arg as NULL (n2 niumx driver) !!! */
 	if (arg2 == NULL || (void *) ldvp->nxgep != arg2) {
 		nxgep = ldvp->nxgep;

usr/src/uts/common/io/nxge/nxge_ipp.c

@@ -766,7 +766,7 @@ nxge_ipp_eccue_valid_check(p_nxge_t nxgep, boolean_t *valid)
 			}
 		}
 
-		if (valid) {
+		if (*valid) {
 			/*
 			 * Further check to see if the ECCUE is valid. The
 			 * error is real if the LSB of d4 is 1, which

usr/src/uts/common/io/nxge/nxge_mac.c

@@ -1540,7 +1540,7 @@ nxge_n2_serdes_init(p_nxge_t nxgep)
 			if ((status = nxge_mdio_write(nxgep, portn,
 			    ESR_N2_DEV_ADDR,
 			    ESR_N2_TEST_CFG_REG, test_cfg.value)) != NXGE_OK)
-			goto fail;
+				goto fail;
 		}
 
 		/* Initialize PLL for 10G */
@@ -2002,7 +2002,7 @@ nxge_n2_kt_serdes_init(p_nxge_t nxgep)
 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
 			    "nxge_n2_kt_serdes_init: "
 			    "Serdes/signal for port<%d> not ready", portn));
-				goto done;
+			goto done;
 		}
 	} else if (portn == 1) {
 		/* Wait for serdes to be ready */
@@ -2031,7 +2031,7 @@ nxge_n2_kt_serdes_init(p_nxge_t nxgep)
 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
 			    "nxge_n2_kt_serdes_init: "
 			    "Serdes/signal for port<%d> not ready", portn));
-				goto done;
+			goto done;
 		}
 	}
 done:
@@ -2519,7 +2519,7 @@ nxge_1G_serdes_init(p_nxge_t nxgep)
 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
 			    "nxge_neptune_1G_serdes_init: "
 			    "Serdes/signal for port<%d> not ready", portn));
-				goto done;
+			goto done;
 		}
 	} else if (portn == 1) {
 		if ((val & ESR_SIG_P1_BITS_MASK_1G) !=
@@ -2533,7 +2533,7 @@ nxge_1G_serdes_init(p_nxge_t nxgep)
 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
 			    "nxge_neptune_1G_serdes_init: "
 			    "Serdes/signal for port<%d> not ready", portn));
-				goto done;
+			goto done;
 
 		}
 	}
@@ -4639,11 +4639,11 @@ nxge_rx_mac_reset(p_nxge_t nxgep)
 	if (nxgep->mac.porttype == PORT_TYPE_XMAC) {
 		if ((rs = npi_xmac_reset(handle, portn, XRX_MAC_RESET_ALL))
 		    != NPI_SUCCESS)
-		goto fail;
+			goto fail;
 	} else {
 		if ((rs = npi_bmac_reset(handle, portn, RX_MAC_RESET))
 		    != NPI_SUCCESS)
-		goto fail;
+			goto fail;
 	}
 
 	NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_rx_mac_reset: port<%d>",
@@ -7124,7 +7124,7 @@ nxge_mac_intr(void *arg1, void *arg2)
 				NXGE_FM_REPORT_ERROR(nxgep, portn, 0,
 				    NXGE_FM_EREPORT_RXMAC_LENGTH_ERRCNT_EXP);
 			}
-			if (status & ICFG_BMAC_RX_VIOL_ERR_CNT_EXP)
+			if (status & ICFG_BMAC_RX_VIOL_ERR_CNT_EXP) {
 				statsp->bmac_stats.rx_viol_err_cnt +=
 				    BMAC_CD_VIO_CNT_MASK;
 				NXGE_FM_REPORT_ERROR(nxgep, portn, 0,
@@ -7155,6 +7155,7 @@ nxge_mac_intr(void *arg1, void *arg2)
 					statsp->bmac_stats.tx_nopause_state++;
 			}
 		}
+	}
 
 	if (ldgp->nldvs == 1) {
 		(void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg,
@@ -7515,7 +7516,7 @@ nxge_hswap_phy_present(p_nxge_t nxgep, uint8_t portn)
 	if (nxge_is_phy_present(nxgep, GOA_CLAUSE45_PORT_ADDR_BASE + portn,
 	    BCM8706_DEV_ID, BCM_PHY_ID_MASK)) {
 		nxgep->xcvr_addr = GOA_CLAUSE45_PORT_ADDR_BASE + portn;
-			goto found_phy;
+		goto found_phy;
 	}
 
 	/*

usr/src/uts/common/io/nxge/nxge_main.c

@@ -3526,14 +3526,14 @@ nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method,
 
 			dma_p->dma_handle = NULL;
 			dma_p->acc_handle = NULL;
-			dma_p->alength = NULL;
+			dma_p->alength = 0;
 			dma_p->kaddrp = NULL;
 
 			return (NXGE_ERROR | NXGE_DDI_FAILED);
 		}
 
 		if (dma_p->ncookies != 1 ||
-		    (dma_p->dma_cookie.dmac_laddress == NULL)) {
+		    (dma_p->dma_cookie.dmac_laddress == 0)) {
 			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
 			    "nxge_dma_mem_alloc:di_dma_addr_bind > 1 "
 			    "cookie or "
@@ -3646,7 +3646,7 @@ nxge_dma_mem_free(p_nxge_dma_common_t dma_p)
 		    dma_p->alength, dma_p->alength));
 
 		contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength);
-		dma_p->orig_alength = NULL;
+		dma_p->orig_alength = 0;
 		dma_p->orig_kaddrp = NULL;
 		dma_p->contig_alloc_type = B_FALSE;
 	}
@@ -3707,11 +3707,11 @@ nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p)
 		kaddr = (uint64_t)dma_p->orig_kaddrp;
 		buf_size = dma_p->orig_alength;
 		nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size);
-		dma_p->orig_alength = NULL;
+		dma_p->orig_alength = 0;
 		dma_p->orig_kaddrp = NULL;
 		dma_p->contig_alloc_type = B_FALSE;
 		dma_p->kaddrp = NULL;
-		dma_p->alength = NULL;
+		dma_p->alength = 0;
 		return;
 	}
 #endif

usr/src/uts/common/io/nxge/nxge_rxdma.c

@@ -3056,10 +3056,11 @@ nxge_rx_err_evnts(p_nxge_t nxgep, int channel, rx_dma_ctl_stat_t cs)
 		NXGE_FM_REPORT_ERROR(nxgep, portn, channel,
 		    NXGE_FM_EREPORT_RDMC_RCRFULL);
 		rxchan_fatal = B_TRUE;
-		if (rdc_stats->rcrfull < error_disp_cnt)
-		NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
-		    "==> nxge_rx_err_evnts(channel %d): "
-		    "fatal error: rcrfull error", channel));
+		if (rdc_stats->rcrfull < error_disp_cnt) {
+			NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL,
+			    "==> nxge_rx_err_evnts(channel %d): "
+			    "fatal error: rcrfull error", channel));
+		}
 	}
 	if (cs.bits.hdw.rbr_empty) {
 		/*

usr/src/uts/common/io/nxge/nxge_send.c

@@ -1219,10 +1219,13 @@ nxge_lso_info_get(mblk_t *mp, uint32_t *mss, uint32_t *flags)
 {
 	ASSERT(DB_TYPE(mp) == M_DATA);
 
+	if (mss == NULL || flags == NULL)
+		return;
+
 	*mss = 0;
 	if (flags != NULL) {
 		*flags = DB_CKSUMFLAGS(mp) & HW_LSO;
-		if ((*flags != 0) && (mss != NULL)) {
+		if (*flags != 0) {
 			*mss = (uint32_t)DB_LSOMSS(mp);
 		}
 		NXGE_DEBUG_MSG((NULL, TX_CTL,