Fix I2C master 2-byte read case.

The master mode on a 2-byte read was incorrectly NAKing prematurely.
As per the ST datasheet for the CR1 register when using read Method 2, it's
very important to clear the ACK bit AFTER clearing the ADDR (not before the
ADDR is cleared!):
  Note: The POS bit is used when the procedure for reception of 2 bytes (see Method 2:
  transfer sequence diagram for master receiver when N=2) is followed. It must be
  configured before data reception starts. In this case, to NACK the 2nd byte, the ACK bit
  must be cleared just after ADDR is cleared. To check the 2nd byte as PEC, the PEC bit
  must be set during the ADDR stretch event after configuring the POS bit.

STM32F1/cores/maple/libmaple/i2c.c

@@ -491,9 +491,9 @@ void _i2c_irq_handler(i2c_dev *dev) {
                             sr2 = dev->regs->SR2;                   // Clear ADDR bit
                             dev->regs->CR1 = (cr1 |= I2C_CR1_STOP); // Stop after last byte
                         } else if (todo == 2) {
-                            dev->regs->CR1 = (cr1 &= ~I2C_CR1_ACK); // Disable ACK
                             dev->regs->CR1 = (cr1 |= I2C_CR1_POS);  // Enable POS
                             sr2 = dev->regs->SR2;                   // Clear ADDR bit
+                            dev->regs->CR1 = (cr1 &= ~I2C_CR1_ACK); // Disable ACK
                         } else {
                             dev->regs->CR1 = (cr1 |= I2C_CR1_ACK);  // Enable ACK
                             sr2 = dev->regs->SR2;                   // Clear ADDR bit