STM32F4 backup domain registers and backup domain sram #850
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STM32F4: update bkp.h, bkp.c add support for backup registers and backup sram. added example in STM32F4/libraries/RTClock/examples/BkpTest
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the comment about this PR : |
updated RTClock.begin() skip initialization of RTC running on LSE if it is already running so that the time maintained on VBAT would not be reset note that the change only prevents resetting RTC on LSE as only that is assured when running on VBAT
in begin()
change:
if(!lse_ison && RTCSEL_LSE) {
to:
if(!lse_ison)
that RTCSEL_LSE is redundant. it suffice to test that lse_ison
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What is actually the status of this PR? |
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this is done back then when I'm trying to use the backup registers on stm32f401. stm32f401 don't have backup sram but that they do have backup registers and this commit is part of works i'm using in some of my sketches to keep some data in the backup registers as these can be safe kept by VBAT (e.g. a coin cell for the RTC) even if the main VDD 3v3 is powered off. I think this shouldn't break anything |
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OK, then I will commit this. |
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thanks ! I'd monitor issues here and in www.stm32duino.com and would respond just in case someone is after all using it |
STM32F4: update bkp.h, bkp.c add support for backup registers and backup sram.
added example in STM32F4/libraries/RTClock/examples/BkpTest