Robotics MCU, an open source software and hardware ROS 2 microcontroller unit (MCU) powered by RISC-V

[vmayoral]

This ticket tracks the progress of the Robotics MCU subproject of the ROS 2 Hardware Acceleration Working Group. Content will be updated as we progress. In time, a repository will branch out of this effort containing additional resources. Expectation however should be for the initial discussion to remain in here for organizational purposes. You can send feedback about this and/or participate by contacting here.

Robotics MCU project

Goal: Design and develop an open source software and hardware robotics microcontroller unit (Robotics MCU) powered by RISC-V that delivers lower latency and additional real-time capabilities in ROS 2 MCU interactions. The ultimate objective of the project is to design an MCU that contains a native ROS 2 hardware implementation.

Project's technical name: robo-v-mcu.

Rationale

A microcontroller (MCU for microcontroller unit) is a small computer that contains one or more CPUs (processor cores) along with memory and programmable input/output peripherals. MCUs are typically more specialized than microprocessors (MPUs, sometimes also known as Application Processing Unit or APUs), as they integrate functions which are specific to a certain domain or area of application. Though microcontrollers are generally accepted as programmable specialized devices, most MCUs used in robotics today have rather general purpose building blocks. There is not much robotics-specific in any of them.

Current popular strategies in robotics for integrating microcontrollers involve complex bridges that break DDS databus interoperability and that introduce undesired delays and much complexity, delivering a hard to optimize and maintain result, namely the micro-ROS project (XRCE-DDS approach). The Robotics MCU project aims to tackle some of the problems identified in the micro-ROS architecture by focusing on 1) enabling ROS 2 direct interoperability from within an open MCU design in the form of a soft-core, 2) performing benchmarks of the resulting design and analyze data together with the micro-ROS approach in both soft and hard-cores, 3) creating a native ROS 2 hardware implementation in an MCU by bringing software layers of the design into IP blocks that can be then transformed into hardware, 4) Customizations of the Instruction Set Architecture (ISA) to optimize ROS 2 operations and 5) prototyping the resulting Robotics MCU design as a hard-core with one of the popular foundries (and currently available programs).

The Robotics MCU subproject will be developed as part of the ROS 2 Hardware Acceleration Working Group and prototyped first into an FPGA and later into a physical chip.

Sponsorship

The project is open to sponsorships and collaborations. For sponsoring the Robotics MCU project contact here.

Technical specs (initial set, may change)

Milestones

• Project announcement and initial planning (this ticket)
• Milestone 1 (ongoing): Robotics MCU as an open RISC-V based MCU design with ROS 2 direct interoperability capabilities (soft-core)
  • phase 1 - hw: CORE-V-MCU adaptation to KR260 (ongoing)
    • 13/12/22: PlanV reported various issues while porting CORE-V-MCU to the target hardware (KR260), looking into those
    • 31/01/23: Issues addressed. Appeared to be glitches while reproducing and flashing things.
  • phase 2 - rtos: FreeRTOS, this might come for free (see demo)
    • 2.1 FreeRTOS validation (see demo)
    • 2.2 Ethernet driver
  • phase 3 - net. stack: lwIP
  • phase 4 - comm. middleware: embeddedRTPS
  • phase 5 - ROS: rmw_embeddedrtps, rmw, rcl, rclc
• Milestone 2: benchmarks of (soft-core) Robotics MCU in an FPGA and comparison with existing alternatives in other soft and hard-cores
• Milestone 3: hardware prototyping the resulting Robotics MCU with a popular foundry/program
• Milestone 4: native ROS 2 hardware implementation by bringing software layers of the design into IP blocks that can be then transformed into hardware (soft-core)
• Milestone 5: customizations of the ISA to optimize ROS 2 operations
• Milestone 6: hardware prototyping 2 the resulting Robotics MCU with a popular foundry/program

[tcal-x]

Hello; there may be some things in common with a project I work on, CFU Playground, which strives to make it easy to add custom extensions to a RISC-V soft core. We use open source IP (e.g. VexRiscv) and open source FPGA tools (Yosys, Nextpnr) where possible, to avoid getting tied to any one FPGA vendor. Our team is also looking at a hardening path involving https://efabless.com/open_shuttle_program using open source ASIC tools (OpenROAD/OpenLane). I'd be happy to chat about these or other alternatives you might consider.

[vmayoral]

Hello; there may be some things in common with a project I work on, CFU Playground, which strives to make it easy to add custom extensions to a RISC-V soft core. We use open source IP (e.g. VexRiscv) and open source FPGA tools (Yosys, Nextpnr) where possible, to avoid getting tied to any one FPGA vendor. Our team is also looking at a hardening path involving https://efabless.com/open_shuttle_program using open source ASIC tools (OpenROAD/OpenLane). I'd be happy to chat about these or other alternatives you might consider.

Thanks @tcal-x, let me have a closer look at those resources. We're also basing ourselves in open source IP (core-v-mcu). I'd be interested in your thoughts here and how it compares to VexRiscv in your experience.

[tcal-x]

Thanks @tcal-x, let me have a closer look at those resources. We're also basing ourselves in open source IP (core-v-mcu). I'd be interested in your thoughts here and how it compares to VexRiscv in your experience.

Yes, the Core-V project has done great work! I've been following their Extension Interface
(https://github.com/openhwgroup/core-v-xif) since it has parallels with the Custom Function Unit (CFU) interface that I use with VexRiscv. I couldn't tell from the core-v-mcu description whether it has an option to incorporate Core-v-xif (like https://github.com/openhwgroup/cv32e40x)

But even without core-v-xif, I think that the Core-V processors are designed to make it easy to add new function units and instructions.

With the VexRiscv, the CPU Verilog is generated from a configuration, so it's very easy to construct an MCU/CPU with exactly the features that you need. You can add the CFU interface to any MCU/CPU, from the smallest MCU class to the largest Linux-capable variant.

The CFU interface implemented by VexRiscv is based on this work, which aims to make it easy to assemble a system with multiple independent custom extensions: https://github.com/grayresearch/CFU. Here's the poster version.

[tcal-x]

@vmayoral another related thing you might find useful (if you don't know about it already) is Antmicro's Renode simulation. It is particularly tuned for embedded MCU systems with multiple nodes, and has strong support for both Arm and RISC-V.

[pablogs9]

Just for curiosity, which DDS/RTPS compatible implementation is going to be used in this project?

[vmayoral]

Just for curiosity, which DDS/RTPS compatible implementation is going to be used in this project?

@pablogs9 we're still discussing and will start prototyping soon. We have some preferences but open to suggestions.

[vmayoral]

@tcal-x I'm still reviewing the material you provided, thanks! Should be able to provide an update to the overall discussion above soon.

[pablogs9]

@pablogs9 we're still discussing and will start prototyping soon. We have some preferences but open to suggestions.

Which are the preferences?

[vmayoral]

Which are the preferences?

@pablogs9, feel free to join the live discussion today https://www.linkedin.com/events/ros2hardwareaccelerationworking6997171083560804352/comments/

[samuk]

Have you considered developing this in a CM4 footprint? You could prototype on https://www.crowdsupply.com/intergalaktik/ulx4m perhaps, then replace the CM4 with your custom hardware later?

Could you clarify which license you will release the hardware design under? The Apache? Had you considered an open-hardware license such as https://ohwr.org/cern_ohl_p_v2.txt

[vmayoral]

This project has been paused because preliminary results obtained didn't suggest it was the best technical choice.

Instead, we re-channeled resources to fully integrate everything into a hardware design (without the use of a custom soft processor core) that runs directly in the FPGA and is built using HDL. Results from this other avenue explored have been disclosed in the form of three IPs: ROBOTCORE UDP/IP, ROBOTCORE RTPS and ROBOTCORE ROS 2. A summary below including block diagrams.

ROBOTCORE UDP/IP	ROBOTCORE RTPS	ROBOTCORE ROS 2
Accelerated UDP/IP networking stack. UDP/IP on FPGA.	Accelerated DDS network communications. DDS-RTPS on FPGA	Accelerated ROS 2 network communications. ROS 2 on FPGA