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SPU LLVM: Use VDBPSADBW in SUMB #10937

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merged 3 commits into from Sep 30, 2021
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6 changes: 6 additions & 0 deletions rpcs3/Emu/CPU/CPUTranslator.h
Expand Up @@ -3564,6 +3564,12 @@ class cpu_translator
{
return llvm_calli<f32[4], T, U>{"llvm.x86.sse.min.ps", {std::forward<T>(a), std::forward<U>(b)}};
}

template <typename T, typename U, typename = std::enable_if_t<std::is_same_v<llvm_common_t<T, U>, u8[16]>>>
static auto vdbpsadbw(T&& a, U&& b, u8 c)
{
return llvm_calli<u8[16], T, U, llvm_const_int<u32>>{"llvm.x86.avx512.dbpsadbw.128", {std::forward<T>(a), std::forward<U>(b), llvm_const_int<u32>{c}}};
}
};

// Format llvm::SizeType
Expand Down
77 changes: 76 additions & 1 deletion rpcs3/Emu/Cell/SPURecompiler.cpp
Expand Up @@ -7022,6 +7022,23 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator

void SUMB(spu_opcode_t op)
{
if (m_use_avx512)
{
const auto [a, b] = get_vrs<u8[16]>(op.ra, op.rb);
const auto zeroes = splat<u8[16]>(0);

if (op.ra == op.rb && !m_interp_magn)
{
set_vr(op.rt, vdbpsadbw(a, zeroes, 0));
return;
}

const auto ax = vdbpsadbw(a, zeroes, 0);
const auto bx = vdbpsadbw(b, zeroes, 0);
set_vr(op.rt, shuffle2(ax, bx, 0, 8, 2, 10, 4, 12, 6, 14));
return;
}

if (m_use_vnni)
{
const auto [a, b] = get_vrs<u32[4]>(op.ra, op.rb);
Expand Down Expand Up @@ -9215,6 +9232,20 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
{
if (m_block) m_block->block_end = m_ir->GetInsertBlock();

const auto rt = get_vr<u8[16]>(op.rt);

// Checking for zero doeesn't care about the order of the bytes,
// so load the data before it's byteswapped
if (auto [ok, as] = match_expr(rt, byteswap(match<u8[16]>())); ok)
{
m_block->block_end = m_ir->GetInsertBlock();
const auto cond = eval(extract(bitcast<u32[4]>(as), 0) == 0);
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
const auto target = add_block_indirect(op, addr);
m_ir->CreateCondBr(cond.value, target, add_block_next());
return;
}

// Check sign bit instead (optimization)
if (match_vr<s32[4], s64[2]>(op.rt, [&](auto c, auto MP)
{
Expand Down Expand Up @@ -9246,6 +9277,21 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
{
if (m_block) m_block->block_end = m_ir->GetInsertBlock();

const auto rt = get_vr<u8[16]>(op.rt);

// Checking for zero doeesn't care about the order of the bytes,
// so load the data before it's byteswapped
if (auto [ok, as] = match_expr(rt, byteswap(match<u8[16]>())); ok)
{
m_block->block_end = m_ir->GetInsertBlock();
const auto cond = eval(extract(bitcast<u32[4]>(as), 0) != 0);
const auto addr = eval(extract(get_vr(op.ra), 3) & 0x3fffc);
const auto target = add_block_indirect(op, addr);
m_ir->CreateCondBr(cond.value, target, add_block_next());
return;
}


// Check sign bit instead (optimization)
if (match_vr<s32[4], s64[2]>(op.rt, [&](auto c, auto MP)
{
Expand Down Expand Up @@ -9466,6 +9512,21 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator

const u32 target = spu_branch_target(m_pos, op.i16);

const auto rt = get_vr<u8[16]>(op.rt);

// Checking for zero doeesn't care about the order of the bytes,
// so load the data before it's byteswapped
if (auto [ok, as] = match_expr(rt, byteswap(match<u8[16]>())); ok)
{
if (target != m_pos + 4)
{
m_block->block_end = m_ir->GetInsertBlock();
const auto cond = eval(extract(bitcast<u32[4]>(as), 0) == 0);
m_ir->CreateCondBr(cond.value, add_block(target), add_block(m_pos + 4));
return;
}
}

// Check sign bit instead (optimization)
if (match_vr<s32[4], s64[2]>(op.rt, [&](auto c, auto MP)
{
Expand Down Expand Up @@ -9510,6 +9571,21 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator

const u32 target = spu_branch_target(m_pos, op.i16);

const auto rt = get_vr<u8[16]>(op.rt);

// Checking for zero doeesn't care about the order of the bytes,
// so load the data before it's byteswapped
if (auto [ok, as] = match_expr(rt, byteswap(match<u8[16]>())); ok)
{
if (target != m_pos + 4)
{
m_block->block_end = m_ir->GetInsertBlock();
const auto cond = eval(extract(bitcast<u32[4]>(as), 0) != 0);
m_ir->CreateCondBr(cond.value, add_block(target), add_block(m_pos + 4));
return;
}
}

// Check sign bit instead (optimization)
if (match_vr<s32[4], s64[2]>(op.rt, [&](auto c, auto MP)
{
Expand Down Expand Up @@ -9566,7 +9642,6 @@ class spu_llvm_recompiler : public spu_recompiler_base, public cpu_translator
m_block->block_end = m_ir->GetInsertBlock();
const auto a = get_vr<s8[16]>(op.rt);
const auto cond = eval((bitcast<s16>(trunc<bool[16]>(a)) & 0x3000) == 0);
//const auto cond = eval((m & 0x3000) == 0);
m_ir->CreateCondBr(cond.value, add_block(target), add_block(m_pos + 4));
return true;
}
Expand Down