remove floating signals

rsarwar87 · Jun 27, 2020 · cb9f7df · cb9f7df
1 parent a61df80
commit cb9f7df
Show file tree

Hide file tree

Showing 3 changed files with 5 additions and 5 deletions.
diff --git a/fpga/cores/dna_reader_v1_0/dna_reader.v b/fpga/cores/dna_reader_v1_0/dna_reader.v
@@ -6,7 +6,7 @@ module dna_reader
   input  wire        aclk,
   input  wire        aresetn,
 
-  output wire [56:0] dna_data
+  output wire [63:0] dna_data
 );
 
   localparam integer CNTR_WIDTH = 16;
@@ -83,6 +83,6 @@ module dna_reader
     end
   end
 
-  assign dna_data = int_data_reg;
+  assign dna_data = {int_data_reg, 7'h0};
 
 endmodule
diff --git a/fpga/cores/dna_reader_v1_0/dna_reader_v1_0.v b/fpga/cores/dna_reader_v1_0/dna_reader_v1_0.v
@@ -6,7 +6,7 @@ module dna_reader
   input  wire        aclk,
   input  wire        aresetn,
 
-  output wire [56:0] dna_data
+  output wire [63:0] dna_data
 );
 
   localparam integer CNTR_WIDTH = 16;
@@ -83,6 +83,6 @@ module dna_reader
     end
   end
 
-  assign dna_data = int_data_reg;
+  assign dna_data = {int_data_reg, 7'h0};
 
 endmodule
diff --git a/fpga/lib/ctl_sts.tcl b/fpga/lib/ctl_sts.tcl
@@ -154,7 +154,7 @@ proc add_status_register {module_name memory_name mclk mrstn {num_ports 32} {int
 
   if {$isZynqMP == 0} {
     connect_pins concat_0/In0 [get_slice_pin dna/dna_data 31 0]
-    connect_pins concat_0/In1 [get_slice_pin dna/dna_data 56 32]
+    connect_pins concat_0/In1 [get_slice_pin dna/dna_data 63 32]
   } else {
     connect_pins concat_0/In0 [get_constant_pin 4222 32]
     connect_pins concat_0/In1 [get_constant_pin 78661 32]