Merge pull request #23 from nmschulte/nms/rusefi-lse-max_wait

LSE max wait patches for rusEFI

os/hal/ports/STM32/STM32F0xx/hal_lld.c

@@ -68,23 +68,30 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif
 
 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;

os/hal/ports/STM32/STM32F0xx/hal_lld.h

@@ -371,6 +371,25 @@
 #define STM32_LSE_ENABLED                   FALSE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   Main clock source selection.
  * @note    If the selected clock source is not the PLL then the PLL is not

os/hal/ports/STM32/STM32F1xx/hal_lld.c

@@ -66,23 +66,30 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif /* STM32_LSE_ENABLED */
 
 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* Prescaler value loaded in registers.*/
     rtc_lld_set_prescaler();

os/hal/ports/STM32/STM32F1xx/hal_lld.h

@@ -172,6 +172,25 @@
 #if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
 #define STM32_LSE_ENABLED           FALSE
 #endif
+
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
 /** @} */
 
 /*===========================================================================*/

os/hal/ports/STM32/STM32F37x/hal_lld.c

@@ -65,23 +65,30 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif
 
 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;

os/hal/ports/STM32/STM32F37x/hal_lld.h

@@ -342,6 +342,25 @@
 #define STM32_LSE_ENABLED                   FALSE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   Main clock source selection.
  * @note    If the selected clock source is not the PLL then the PLL is not

os/hal/ports/STM32/STM32F3xx/hal_lld.c

@@ -65,23 +65,30 @@ static void hal_lld_backup_domain_init(void) {
 
   /* If enabled then the LSE is started.*/
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif
 
 #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;

os/hal/ports/STM32/STM32F3xx/hal_lld.h

@@ -382,6 +382,25 @@
 #define STM32_LSE_ENABLED                   FALSE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   Main clock source selection.
  * @note    If the selected clock source is not the PLL then the PLL is not

os/hal/ports/STM32/STM32F4xx/hal_lld.c

@@ -64,23 +64,30 @@ static void hal_lld_backup_domain_init(void) {
   }
 
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif
 
 #if HAL_USE_RTC
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;

os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h

@@ -620,6 +620,25 @@
 #define STM32_LSE_ENABLED           FALSE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   USB/SDIO clock setting.
  */

os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h

@@ -402,6 +402,25 @@
 #define STM32_LSE_ENABLED           FALSE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   USB/SDIO clock setting.
  */

os/hal/ports/STM32/STM32F7xx/hal_lld.c

@@ -64,23 +64,30 @@ static void hal_lld_backup_domain_init(void) {
   }
 
 #if STM32_LSE_ENABLED
+  int rusefiLseCounter = 0;
 #if defined(STM32_LSE_BYPASS)
   /* LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
 #else
   /* No LSE Bypass.*/
   RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
 #endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                       /* Waits until LSE is stable.   */
+  /* Waits until LSE is stable or times out. */
+  while ((!RUSEFI_STM32_LSE_WAIT_MAX || rusefiLseCounter++ < RUSEFI_STM32_LSE_WAIT_MAX)
+      && (RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;
 #endif
 
 #if HAL_USE_RTC
   /* If the backup domain hasn't been initialized yet then proceed with
      initialization.*/
   if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
     /* Selects clock source.*/
+#if STM32_LSE_ENABLED
+    RCC->BDCR |= (RCC->BDCR & RCC_BDCR_LSERDY) == 0 ? RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL : STM32_RTCSEL;
+#else
     RCC->BDCR |= STM32_RTCSEL;
+#endif
 
     /* RTC clock enabled.*/
     RCC->BDCR |= RCC_BDCR_RTCEN;

os/hal/ports/STM32/STM32F7xx/hal_lld.h

@@ -513,6 +513,25 @@
 #define STM32_LSE_ENABLED                   TRUE
 #endif
 
+/**
+ * @brief   Number of times to busy-loop waiting for LSE clock source.
+ * @note    The default value of 0 disables this behavior.
+ * @note    See also RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX           0
+#endif
+
+/**
+ * @brief   Fallback RTC clock source if stopped waiting for LSE clock source.
+ * @note    If waiting for the LSE clock source times out due to
+ *          RUSEFI_STM32_LSE_WAIT_MAX, this allows the RTC clock source to
+ *          fallback to another.
+ */
+#if !defined(RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL) || defined(__DOXYGEN__)
+#define RUSEFI_STM32_LSE_WAIT_MAX_RTCSEL    STM32_RTCSEL_LSE
+#endif
+
 /**
  * @brief   USB/SDIO clock setting.
  */