should work now (Nightly e4ca1662f 2021-05-22)

[Lokathor]

Closes #141

[Lokathor]

@Lymia please double check that I adjusted the assembly correctly <3

[Lymia]

Ah. The idea here is that the copy happens in one instruction either way, because (AFAIK) interrupts cannot happen in the middle of an instruction. Instead of adding pushes (which theoretically would allow an interrupt to happen between the push and the stmia), what you want to do instead is remove r9 from every case that has it, then just remove one case off the end, and make larger structs use the slow path instead.

[Lokathor]

The new push/pop of r9 is just because we can't automatically trash r9 during our assembly block. LLVM itself might be using it and for reasons I don't fully follow inline-asm can't auto push/pop that register when necessary any more (zulip). The fact that we were allowed to use r9 before was a bug in inline-asm. Once they fixed that bug, we just have to save/restore the value of r9 ourselves.

However, my understanding is that even if we're saving and restoring that register manually instead of automatically, the fundamental logic of the near-atomic nature of a load-multi and then store-multi holds. An interrupt can't happen during a store-multi operation, so either it interrupts before the store-multi or after it, but the memory will be consistent either way.

[Lymia]

Oh! Aha, I misunderstood what you did. You're saving and restoring r9 but leaving the actual store operation the same. Just saving it on the stack. I hadn't thought of doing that before, and it makes a great deal of sense. I like it. This should work perfectly.

[Lokathor]

Also, why are we skipping over r6, r7, and r11 when picking registers for the load-multi/store-multi? Are they also special registers?

[Lymia]

IIRC, I tried them and they gave me errors. I think so. For all I know, the PR has changed which registers are considered special, and some of them are available now.

[Lokathor]

good enough! we can investigate that later.