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should work now (Nightly e4ca1662f 2021-05-22) #149
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@Lymia please double check that I adjusted the assembly correctly <3 |
Ah. The idea here is that the copy happens in one instruction either way, because (AFAIK) interrupts cannot happen in the middle of an instruction. Instead of adding pushes (which theoretically would allow an interrupt to happen between the push and the stmia), what you want to do instead is remove |
The new push/pop of However, my understanding is that even if we're saving and restoring that register manually instead of automatically, the fundamental logic of the near-atomic nature of a load-multi and then store-multi holds. An interrupt can't happen during a store-multi operation, so either it interrupts before the store-multi or after it, but the memory will be consistent either way. |
Oh! Aha, I misunderstood what you did. You're saving and restoring |
Also, why are we skipping over r6, r7, and r11 when picking registers for the load-multi/store-multi? Are they also special registers? |
IIRC, I tried them and they gave me errors. I think so. For all I know, the PR has changed which registers are considered special, and some of them are available now. |
good enough! we can investigate that later. |
Closes #141