Merge #37

37: Add support for custom vexriscv instructions r=Disasm a=xobs

This adds a new namespace under "registers" to support the custom interrupt controller on vexriscv.

Co-authored-by: Sean Cross <sean@xobs.io>

asm.S

@@ -273,3 +273,10 @@ RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
 RW(0x7B0, dcsr)     // Debug control and status register
 RW(0x7B1, dpc)      // Debug PC
 RW(0x7B2, dscratch) // Debug scratch register
+
+// VexRiscv custom registers
+RW(0xBC0, vmim)     // Machine IRQ Mask
+RO(0xFC0, vmip)     // Machine IRQ Pending
+RW(0x9C0, vsim)     // Supervisor IRQ Mask
+RO(0xDC0, vsip)     // Supervisor IRQ Pending
+RO(0xCC0, vdci)     // DCache Info

assemble.ps1

@@ -0,0 +1,19 @@
+New-Item -Force -Name bin -Type Directory
+
+# remove existing blobs because otherwise this will append object files to the old blobs
+Remove-Item -Force bin/*.a
+
+$crate = "riscv"
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32i asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32i-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32 -march=rv32imc asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32imc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64imac asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64imac-unknown-none-elf.a bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64gc-unknown-none-elf.a bin/$crate.o
+
+Remove-Item bin/$crate.o

src/register/mod.rs

@@ -108,3 +108,7 @@ pub use self::mhpmeventx::*;
 
 
 // TODO: Debug Mode Registers
+
+
+// Vexriscv custom CSRs
+pub mod vexriscv;

src/register/vexriscv/dci.rs

@@ -0,0 +1,10 @@
+//! vexriscv dci register -- dcache info
+//!
+//! This register is only available if the core was built with
+//! `DBusCachedPlugin` enabled and `csrInfo` set to `true`.
+//!
+//! See
+//! [DBusCachedPlugin.scala](https://github.com/SpinalHDL/VexRiscv/blob/95237b23ea2d658cb3e0aa77680ca2851ef5d882/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala#L358)
+//! for more information.
+
+read_csr_as_usize!(0xCC0, __read_vdci);

src/register/vexriscv/mim.rs

@@ -0,0 +1,4 @@
+//! vexriscv mim register -- machine irq mask
+
+read_csr_as_usize!(0xBC0, __read_vmim);
+write_csr_as_usize!(0xBC0, __write_vmim);

src/register/vexriscv/mip.rs

@@ -0,0 +1,3 @@
+//! vexriscv mip register -- machine irq pending
+
+read_csr_as_usize!(0xFC0, __read_vmip);

src/register/vexriscv/mod.rs

@@ -0,0 +1,13 @@
+//! VexRiscv CSRs
+//!
+//! [VexRiscv](https://github.com/SpinalHDL/VexRiscv) is a RISC-V softcore
+//! written in Scala.  It is highly configurable, and can be built with features
+//! such as a dcache and an external interrupt controller.
+//!
+//! These features use vendor-specific CSRs, which are available using this
+//! module.
+pub mod dci;
+pub mod mim;
+pub mod mip;
+pub mod sim;
+pub mod sip;

src/register/vexriscv/sim.rs

@@ -0,0 +1,4 @@
+//! vexriscv sim register -- supervisor irq mask
+
+read_csr_as_usize!(0x9C0, __read_vsim);
+write_csr_as_usize!(0x9C0, __write_vsim);

src/register/vexriscv/sip.rs

@@ -0,0 +1,3 @@
+//! vexriscv sip register -- supervisor irq pending
+
+read_csr_as_usize!(0xDC0, __read_vsip);