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add Thumbs to the compiler #36874

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merged 8 commits into from Oct 4, 2016

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commented Sep 30, 2016

this commit adds 4 new target definitions to the compiler for easier
cross compilation to ARM Cortex-M devices.

  • thumbv6m-none-eabi
    • For the Cortex-M0, Cortex-M0+ and Cortex-M1
    • This architecture doesn't have hardware support (instructions) for
      atomics. Hence, the Atomic* structs are not available for this
      target.
  • thumbv7m-none-eabi
    • For the Cortex-M3
  • thumbv7em-none-eabi
    • For the FPU-less variants of the Cortex-M4 and Cortex-M7
    • On this target, all the floating point operations will be lowered
      software routines (intrinsics)
  • thumbv7em-none-eabihf
    • For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU.
    • On this target, all the floating point operations will be lowered
      to hardware instructions

No binary releases of standard crates, like core, are planned for
these targets because Cargo, in the future, will compile e.g. the core
crate on the fly as part of the cargo build process. In the meantime,
you'll have to compile the core crate yourself. Xargo is the easiest
way to do that as in handles the compilation of core automatically and
can be used just like Cargo: xargo build --target thumbv6m-none-eabi
is all that's needed.


cc @brson @alexcrichton

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commented Sep 30, 2016

Thanks for the pull request, and welcome! The Rust team is excited to review your changes, and you should hear from @arielb1 (or someone else) soon.

If any changes to this PR are deemed necessary, please add them as extra commits. This ensures that the reviewer can see what has changed since they last reviewed the code. Due to the way GitHub handles out-of-date commits, this should also make it reasonably obvious what issues have or haven't been addressed. Large or tricky changes may require several passes of review and changes.

Please see the contribution instructions for more information.

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commented Sep 30, 2016

👍
👎

@japaric
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Oh, I meant to left this comment earlier but didn't realize I clicked the start review thing. :facepalm:

@@ -698,6 +707,10 @@ impl ToJson for Target {
target_option_val!(max_atomic_width);
target_option_val!(panic_strategy);

if self.options.max_atomic_width.to_string() != self.target_pointer_width {

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japaric Sep 30, 2016

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@alexcrichton this fixes the problem I was seeing where setting max_atomic_width to 0 in the Target declaration was being converted into 32 due to the JSON roundtrip. I've also added a rmake test for this.

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@Ericson2314

Ericson2314 Oct 2, 2016

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Woah can't we use Option instead of magic 0 treatment or similar? Granted, I'm arriving late to this issue so apologies if that has already been ruled out for good reason.

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japaric Oct 4, 2016

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This was the simplest change necessary to make this work but using Option here sounds better; I'll give it a try.

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commented Oct 1, 2016

☔️ The latest upstream changes (presumably #36339) made this pull request unmergeable. Please resolve the merge conflicts.

japaric added 4 commits Sep 16, 2016
add Thumbs to the compiler
this commit adds 4 new target definitions to the compiler for easier
cross compilation to ARM Cortex-M devices.

- `thumbv6m-none-eabi`
  - For the Cortex-M0, Cortex-M0+ and Cortex-M1
  - This architecture doesn't have hardware support (instructions) for
    atomics. Hence, the `Atomic*` structs are not available for this
    target.
- `thumbv7m-none-eabi`
  - For the Cortex-M3
- `thumbv7em-none-eabi`
  - For the FPU-less variants of the Cortex-M4 and Cortex-M7
  - On this target, all the floating point operations will be lowered
    software routines (intrinsics)
- `thumbv7em-none-eabihf`
  - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU.
  - On this target, all the floating point operations will be lowered
    to hardware instructions

No binary releases of standard crates, like `core`, are planned for
these targets because Cargo, in the future, will compile e.g. the `core`
crate on the fly as part of the `cargo build` process. In the meantime,
you'll have to compile the `core` crate yourself. [Xargo] is the easiest
way to do that as in handles the compilation of `core` automatically and
can be used just like Cargo: `xargo build --target thumbv6m-none-eabi`
is all that's needed.

[Xargo]: https://crates.io/crates/xargo

@japaric japaric force-pushed the japaric:thumbs branch from d44bdc5 to 6d0b8ae Oct 2, 2016

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commented Oct 2, 2016

Pushed two new commits. The first changes relocation-model to static (from pic) and the second changes panic-strategy to abort (from unwind). These values differ from the RFC text but I asked about these changes in the associated PR and the response has been positive so far.


options: TargetOptions {
// vfp4 lowest common denominator between the Cortex-M4 (vfp4) and the Cortex-M7 (vfp5)
features: "+vfp4".to_string(),

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parched Oct 2, 2016

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I believe you also need +fp-only-sp

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japaric Oct 2, 2016

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Hmm, won't that preclude a user from enabling double precision hardware acceleration? Perhaps they'll have to pass -fp-only-sp apart from the other feature that enables DP FP ops. (I'm speculating; I haven't tried any of this)

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parched Oct 3, 2016

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Yes -fp-only-sp would work to switch it back on. +d16 should probably be added here too.

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japaric Oct 4, 2016

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Done! Thank you @parched.

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commented Oct 3, 2016

@japaric could you also add some comments to each target file in line with the RFC itself? Basically just some basic rationale for the target name, what it's intended to be used for, etc.

@alexcrichton alexcrichton assigned alexcrichton and unassigned arielb1 Oct 3, 2016

japaric added 4 commits Oct 4, 2016
change max_atomic_width type from u64 to Option<u64>
to better express the idea that omitting this field defaults this value
to target_pointer_width
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commented Oct 4, 2016

@bors: r+

Thanks @japaric!

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commented Oct 4, 2016

📌 Commit 6136069 has been approved by alexcrichton

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commented Oct 4, 2016

⌛️ Testing commit 6136069 with merge a5dac7a...

bors added a commit that referenced this pull request Oct 4, 2016
Auto merge of #36874 - japaric:thumbs, r=alexcrichton
add Thumbs to the compiler

this commit adds 4 new target definitions to the compiler for easier
cross compilation to ARM Cortex-M devices.

- `thumbv6m-none-eabi`
  - For the Cortex-M0, Cortex-M0+ and Cortex-M1
  - This architecture doesn't have hardware support (instructions) for
    atomics. Hence, the `Atomic*` structs are not available for this
    target.
- `thumbv7m-none-eabi`
  - For the Cortex-M3
- `thumbv7em-none-eabi`
  - For the FPU-less variants of the Cortex-M4 and Cortex-M7
  - On this target, all the floating point operations will be lowered
    software routines (intrinsics)
- `thumbv7em-none-eabihf`
  - For the variants of the Cortex-M4 and Cortex-M7 that do have a FPU.
  - On this target, all the floating point operations will be lowered
    to hardware instructions

No binary releases of standard crates, like `core`, are planned for
these targets because Cargo, in the future, will compile e.g. the `core`
crate on the fly as part of the `cargo build` process. In the meantime,
you'll have to compile the `core` crate yourself. [Xargo] is the easiest
way to do that as in handles the compilation of `core` automatically and
can be used just like Cargo: `xargo build --target thumbv6m-none-eabi`
is all that's needed.

[Xargo]: https://crates.io/crates/xargo

---

cc @brson @alexcrichton

@bors bors merged commit 6136069 into rust-lang:master Oct 4, 2016

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@japaric japaric deleted the japaric:thumbs branch Oct 4, 2016

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