Welcome to my GitHub profile! I'm Soroush Javed Sulehri, a recent graduate in Electrical Engineering from the Pakistan Institute of Engineering and Applied Sciences (PIEAS), with a strong focus on embedded systems, FPGA-based digital signal processing, and algorithm optimization through parallel computing.

I am passionate about accelerating computational tasks using heterogeneous computing systems, with a particular interest in applying these techniques to genome sequence analysis, digital signal processing, and embedded system design. My work spans from implementing and optimizing algorithms on FPGAs and cloud platforms to developing real-time embedded systems.

• C/C++: Advanced proficiency, particularly in system programming and algorithm development.
• Python: Strong expertise in data analysis, machine learning, and scripting.
• MATLAB: Extensive experience in digital signal processing and numerical analysis.
• Rust: Knowledgeable in system-level programming.
• JavaScript: Web development, particularly for creating dynamic and interactive websites.

• Verilog/SystemVerilog: Proficient in designing and simulating digital circuits.
• VHDL: Experience in hardware design and verification.

• Xilinx ISE/Vivado: Expertise in FPGA design, synthesis, and implementation.
• ModelSim: Simulation and verification of digital circuits.
• Keil MicroVision: Embedded systems development on ARM Cortex-M microcontrollers.
• FreeRTOS: Real-time operating system for embedded applications.
• Arduino/STM32: Embedded systems prototyping and development.

• LaTeX: Proficient in creating well-structured technical documents and reports.
• Pandas, NumPy, SciPy: Skilled in data manipulation and analysis.
• Excel: Advanced data handling and visualization.

• Digital Signal Processing: Design and implementation of FFTs, filters, and other DSP algorithms.
• Parallel Computing: Optimization of algorithms for multi-core processors and FPGAs.
• Web Development: Front-end development using HTML, CSS, and JavaScript.

• Sneaky Snake Algorithm: Implemented and optimized the Sneaky Snake pre-alignment filtering algorithm on CPU, FPGA, and cloud platforms. This project was part of my final year thesis and explored the performance improvements achievable through heterogeneous computing.

• 4-bit ALU Design: Designed and implemented a 4-bit ALU on the Spartan-3E FPGA, supporting 16 arithmetic and logical operations. This project involved extensive testing and verification using both simulation and physical hardware.

• Real-Time Compression using FFT: Developed a FreeRTOS-based compression algorithm using Fast Fourier Transform on an Arduino platform.

I have had the opportunity to present my research at international conferences, showcasing my work in accelerating computational algorithms and optimizing performance through innovative hardware and software solutions:

• IEEE International Bhuban Conference on Applied Sciences & Technology (IBCAST 2024): Presented a paper titled "Accelerating Genome Sequence Analysis via Pre-alignment Filtering: A Review of Sneaky Snake Algorithm." The research focuses on the performance gains achieved by implementing the Sneaky Snake algorithm on various platforms, including CPUs, FPGAs, and cloud computing environments. This paper is currently under review for publication on IEEE Xplore.

Here on GitHub, I share my projects, from hardware implementations on FPGAs to software applications in Python and C++. My repositories reflect my ongoing efforts to explore and innovate within the fields of embedded systems, digital signal processing, and parallel computing.

Feel free to explore my repositories, and don't hesitate to reach out if you're interested in collaboration or have any questions!

• Email: soroushjaved@gmail.com

Thank you for visiting my profile! If you find my work interesting, consider following me or starring my repositories. Let's build something innovative together!